Reduction of severe bovine serum associated matrix effects on carboxymethylated dextran coated biosensor surfaces

Surface plasmon resonance (SPR) based biosensor technology has been widely used in life science research for many applications. While the advantages of speed, ruggedness, versatility, sensitivity and reproducibility are often quoted, many researchers have experienced severe problem of non-specific binding (NSB) to chip surfaces when performing analysis of biological samples Such as bovine serum. Using the direct measurement of the bovine protein leptin, present in bovine serum samples as a model, a unique buffering system has been developed and optimised which was able to significantly reduce the non-specific interactions of bovine serum components with the carboxymethyl dextran chip (CM5) surface on a Biacore SPR The developed NSB buffering system comprised of HBS-EP buffer, containing 0.5 M NaCl, 0.005% CM-dextran pH 9.0. An average NSB reduction (n = 20) of 85.9% and 87.3% was found on an unmodified CM5 surface and a CM5 with bovine leptin immobilised on the chip surface, respectively. A reduction in NSB of up to 94% was observed on both surfaces. The concentration of the constitutive components and pH of the buffer were crucial in achieving this outcome. (C) 2008 Elsevier B.V. All rights reserved.

High-Speed Fully Homomorphic Encryption Over the Integers

A fully homomorphic encryption (FHE) scheme is envisioned as a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrary evaluation of a ciphertext without revealing the plaintext. However, existing FHE implementations remain impractical due to very high time and resource costs. To the authors’ knowledge, this paper presents the first hardware implementation of a full encryption primitive for FHE over the integers using FPGA technology. A large-integer multiplier architecture utilising Integer-FFT multiplication is proposed, and a large-integer Barrett modular reduction module is designed incorporating the proposed multiplier. The encryption primitive used in the integer-based FHE scheme is designed employing the proposed multiplier and modular reduction modules. The designs are verified using the Xilinx Virtex-7 FPGA platform. Experimental results show that a speed improvement factor of up to 44 is achievable for the hardware implementation of the FHE encryption scheme when compared to its corresponding software implementation. Moreover, performance analysis shows further speed improvements of the integer-based FHE encryption primitives may still be possible, for example through further optimisations or by targeting an ASIC platform.