Novel Radio Link Buffer Management Schemes for End-User Multi-class Traffic in High Speed Packet Access Networks

The requirement to provide multimedia services with QoS support in mobile networks has led to standardization and deployment of high speed data access technologies such as the High Speed Downlink Packet Access (HSDPA) system. HSDPA improves downlink packet data and multimedia services support in WCDMA-based cellular networks. As is the trend in emerging wireless access technologies, HSDPA supports end-user multi-class sessions comprising parallel flows with diverse Quality of Service (QoS) requirements, such as real-time (RT) voice or video streaming concurrent with non real-time (NRT) data service being transmitted to the same user, with differentiated queuing at the radio link interface. Hence, in this paper we present and evaluate novel radio link buffer management schemes for QoS control of multimedia traffic comprising concurrent RT and NRT flows in the same HSDPA end-user session. The new buffer management schemes—Enhanced Time Space Priority (E-TSP) and Dynamic Time Space Priority (D-TSP)—are designed to improve radio link and network resource utilization as well as optimize end-to-end QoS performance of both RT and NRT flows in the end-user session. Both schemes are based on a Time-Space Priority (TSP) queuing system, which provides joint delay and loss differentiation between the flows by queuing (partially) loss tolerant RT flow packets for higher transmission priority but with restricted access to the buffer space, whilst allowing unlimited access to the buffer space for delay-tolerant NRT flow but with queuing for lower transmission priority. Experiments by means of extensive system-level HSDPA simulations demonstrates that with the proposed TSP-based radio link buffer management schemes, significant end-to-end QoS performance gains accrue to end-user traffic with simultaneous RT and NRT flows, in addition to improved resource utilization in the radio access network.

Integration of design of experiment, surface response methodology and multi-layer validation to predict the effect of blanching on colour of tomato juice

Response surface methodology was used to develop models to predict the effect of tomato cultivar, juice pH, blanching temperature and time on colour change of tomato juice after blanching. The juice from three tomato cultivars with adjusted pH levels ranging from 3.9 to 4.6 were blanched at temperatures from 60-100 °C for 1-5 min using the central composite design (CCD). The colour change was assessed by calculating the redness (a/b) and total colour change (∆E) after measuring the Hunter L, a and b values. Developed models for both redness and ∆E were significant (p<0.0001) with satisfactory coefficient of determination (R2 = 0.99 and 0.97) and low coefficient of variation (CV% = 1.89 and 7.23), respectively. Multilevel validation that was implemented revealed that the variation between the predicted and experimental values obtained for redness and ∆E were within the acceptable error range of 7.3 and 22.4%, respectively

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Graphical determination of network limits for wind power integration

A graphical method is presented for determining the capability of individual system nodes to accommodate wind power generation. The method is based upon constructing a capability chart for each node at which a wind farm is to be connected. The capability chart defines the domain of allowable power injections at the candidate node, subject to constraints imposed by voltage limits, voltage stability and equipment capability limits being satisfied. The chart is first derived for a two-bus model, before being extended to a multi-node power system. The graphical method is employed to derive the chart for a two-node system, as well as its application to a multi-node power system, considering the IEEE 30-bus test system as a case study. Although the proposed method is derived with the intention of determining the wind farm capacity to be connected at a specific node, it can be used for the analysis of a PQ bus loading as well as generation.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Party organisation in a multi-level system: Party organisational change in Spain and the UK

This article investigates the link between regionalization of the structure of government, regional elections and regionalism on the one hand, and the organization of state-wide political parties in Spain and the UK on the other. It particularly looks at two aspects of the relations between the central and regional levels of party organization: integration of the regional branches in central decision making and autonomy of the regional branches. It argues that the party factors are the most crucial elements explaining party change and that party leaders mediate between environmental changes and party organization. The parties' history and beliefs and the strength of the central leadership condition their ability or willingness to facilitate the emergence of meso-level elites. The institutional and electoral factors are facilitating factors that constitute additional motives for or against internal party decentralization.

End-to-End QoS Enhancement ofHSDPA End-User Multi-flow Traffic Using RAN Buffer Management

High speed downlink packet access (HSDPA) was introduced to UMTS radio access segment to provide higher capacity for new packet switched services. As a result, packet switched sessions with multiple diverse traffic flows such as concurrent voice and data, or video and data being transmitted to the same user are a likely commonplace cellular packet data scenario. In HSDPA, radio access network (RAN) buffer management schemes are essential to support the end-to-end QoS of such sessions. Hence in this paper we present the end-to-end performance study of a proposed RAN buffer management scheme for multi-flow sessions via dynamic system-level HSDPA simulations. The scheme is an enhancement of a time-space priority (TSP) queuing strategy applied to the node B MAC-hs buffer allocated to an end user with concurrent real-time (RT) and non-real-time (NRT) flows during a multi-flow session. The experimental multi- flow scenario is a packet voice call with concurrent TCP-based file download to the same user. Results show that with the proposed enhancements to the TSP-based RAN buffer management, end-to-end QoS performance gains accrue to the NRT flow without compromising RT flow QoS of the same end user session