Design optimisation of ring elements for broadband reflectarray antennas

Plane wave scattering from a flat surface consisting of two periodic arrays of ring elements printed on a grounded dielectric sheet is investigated. It is shown that the reflection phase variation as a function of ring diameter is controlled by the difference in the centre resonant frequency of the two arrays. Simulated and measured results at X-band demonstrate that this parameter can be used to reduce the gradient and improve the linearity of the reflection phase versus ring size slope. These are necessary conditions for the re-radiating elements to maximise the bandwidth of a microstrip reflectarray antenna. The scattering properties of a conventional dual resonant multilayer structure and an array of concentric rings printed on a metal backed dielectric substrate are compared and the trade-off in performance is discussed.

The Region between State and Nation: British and Irish conceptions of Northern Ireland as a European Region

This article investigates the concept of regionalism in the EU and its relationship to changing conceptions of the nation-statehood in Ireland and Britain. More specifically, it examines how the notion of regionalism has developed in official discourse during states' adaptation to both internal challenges and the process of European integration. I explore this question through an analysis of the British and Irish state elites approaches to the Northern Ireland conflict and their perceptions of European regionalism in this context. In identifying the differences and, indeed, similarities between these states' approaches to European and regional dynamics, I develop new perspective on post-Agreement Northern Ireland and the concept of multilevel governance.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.