Equivalent Circuit Model of Twisted Split Ring Frequency Selective Surfaces

This paper proposes a wideband equivalent circuit model for a twisted split ring frequency selective surface (FSS). Such surfaces can be used for modelling and design of polarisation sensitive surfaces such as circularly polarized selective surfaces as well as structures with asymmetric transmission. The proposed model is based extraction of equivalent circuit parameters from a single split ring (SRR) FSS and magnetic coupling from periodic eigenmode analysis of the coupled SRR. The resulting equivalent circuit model demonstrates excellent agreement with full-wave simulations.

Physical model parameter optimisation for calibrated emulation of the Dallas Rangemaster Treble Booster guitar pedal

In this work we explore optimising parameters of a physical circuit model relative to input/output measurements, using the Dallas Rangemaster Treble Booster as a case study. A hybrid metaheuristic/gradient descent algorithm is implemented, where the initial parameter sets for the optimisation are informed by nominal values from schematics and datasheets. Sensitivity analysis is used to screen parameters, which informs a study of the optimisation algorithm against model complexity by fixing parameters. The results of the optimisation show a significant increase in the accuracy of model behaviour, but also highlight several key issues regarding the recovery of parameters.

Mutual impedance between two dipole antennas fed by single source

We present a new circuit-model approach which can be used to compute the mutual impedance between two dipoles fed at the same feed point. The validity of the method is confirmed by comparison with mutual impedance values obtained when the dipoles are individually excited and orientated at angles between 0degrees and 90degrees. (C) 2004 Wiley Periodicals, Inc.

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. in order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small-signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y-parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S-22 in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright (C) 2006 John Wiley & Sons, Ltd.

Electro-thermal theory of intermodulation distortion in lossy microwave components

An analytic formulation of dynamic electro-thermally induced nonlinearity is developed for a general resistive element, yielding a self-heating circuit model based on a fractional derivative. The model explains the 10 dB/decade slope of the intermodulation products observed in two-tone testing. Two-tone testing at 400 MHz of attenuators, microwave chip terminations, and coaxial terminations is reported with tone spacing ranging from 1 to 100 Hz.

Power Stored and Quality Factors in Frequency Selective Surfaces at THz Frequencies

A study of the external, loaded and unloaded quality factors for frequency selective surfaces (FSSs) is presented. The study is focused on THz frequencies between 5 and 30 THz, where ohmic losses arising from the conductors become important. The influence of material properties, such as metal thickness, conductivity dispersion and surface roughness, is investigated. An equivalent circuit that models the FSS in the presence of ohmic losses is introduced and validated by means of full-wave results. Using both full-wave methods as well as a circuit model, the reactive energy stored in the vicinity of the FSS at resonance upon plane-wave incidence is presented. By studying a doubly periodic array of aluminium strips, it is revealed that the reactive power stored at resonance increases rapidly with increasing periodicity. Moreover, it is demonstrated that arrays with larger periodicity-and therefore less metallisation per unit area-exhibit stronger thermal absorption. Despite this absorption, arrays with higher periodicities produce higher unloaded quality factors. Finally, experimental results of a fabricated prototype operating at 14 THz are presented.

Design Method for Circularly Polarized Frequency Selective Surfaces

This paper proposes a design method for the realisation of circularly polarised frequency selective surfaces (CP FSS). An equivalent circuit model for a capacitive asymmetric loop FSS is proposed. For this model a set of nonlinear design equation for CP operation is obtained. Based on space mapping of the model and full-wave simulation, a fast converging design method for CP FSS synthesis is demonstrated for the first time. 

External circuit system effects on chlorine plasma instabilities

The effects of the external circuit on plasma instabilities in all inductive plasma source are investigated. The instabilities are found to be asymmetric with respect to the circuit input impedance. A simplified model of the antenna-plasnia coupling provides an explanation of the asymetry.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3x faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

Non-Markovian qubit dynamics in a circuit-QED setup

We consider a circuit-QED setup that allows the induction and control of non-Markovian dynamics of a qubit. Non-Markovianity is enforced over the qubit by means of its direct coupling to a bosonic mode which is controllably coupled to another qubit-mode system. We show that this configuration can be achieved in a circuit-QED setup consisting of two initially independent superconducting circuits, each formed by one charge qubit and one transmission-line resonator, which are put in interaction by coupling the resonators to a current-biased Josephson junction. We solve this problem exactly and then proceed with a thorough investigation of the emergent non-Markovianity in the dynamics of the qubits. Our study might serve the context for the first experimental assessment of non-Markovianity in a multielement solid-state device.

An integrated approach for real-time model-based state-of-charge estimation of lithium-ion batteries

Lithium-ion batteries have been widely adopted in electric vehicles (EVs), and accurate state of charge (SOC) estimation is of paramount importance for the EV battery management system. Though a number of methods have been proposed, the SOC estimation for Lithium-ion batteries, such as LiFePo4 battery, however, faces two key challenges: the flat open circuit voltage (OCV) vs SOC relationship for some SOC ranges and the hysteresis effect. To address these problems, an integrated approach for real-time model-based SOC estimation of Lithium-ion batteries is proposed in this paper. Firstly, an auto-regression model is adopted to reproduce the battery terminal behaviour, combined with a non-linear complementary model to capture the hysteresis effect. The model parameters, including linear parameters and non-linear parameters, are optimized off-line using a hybrid optimization method that combines a meta-heuristic method (i.e., the teaching learning based optimization method) and the least square method. Secondly, using the trained model, two real-time model-based SOC estimation methods are presented, one based on the real-time battery OCV regression model achieved through weighted recursive least square method, and the other based on the state estimation using the extended Kalman filter method (EKF). To tackle the problem caused by the flat OCV-vs-SOC segments when the OCV-based SOC estimation method is adopted, a method combining the coulombic counting and the OCV-based method is proposed. Finally, modelling results and SOC estimation results are presented and analysed using the data collected from LiFePo4 battery cell. The results confirmed the effectiveness of the proposed approach, in particular the joint-EKF method.

Circuit-aware design of energy-efficient massive MIMO systems

Densification is a key to greater throughput in cellular networks. The full potential of coordinated multipoint (CoMP) can be realized by massive multiple-input multiple-output (MIMO) systems, where each base station (BS) has very many antennas. However, the improved throughput comes at the price of more infrastructure; hardware cost and circuit power consumption scale linearly/affinely with the number of antennas. In this paper, we show that one can make the circuit power increase with only the square root of the number of antennas by circuit-aware system design. To this end, we derive achievable user rates for a system model with hardware imperfections and show how the level of imperfections can be gradually increased while maintaining high throughput. The connection between this scaling law and the circuit power consumption is established for different circuits at the BS.