27 resultados para Unbalanced Circuits

em QUB Research Portal - Research Directory and Institutional Repository for Queen's University Belfast


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A power combining strategy for Class-E and inverse Class-E amplifiers operating at high frequencies such that they can operate into unbalanced loads is proposed. This power combining method is particularly important for the inverse Class-E amplifier configuration whose single-stage topology is naturally limited for small-to-medium power applications. Design examples for the power combining synthesis of classical Class-E and then inverse Class-E amplifiers with specification 3 V-1.5 W-2.5 GHz are given. For this specification, it is shown that a three-branch combiner has a natural 50 V output impedance. The resulting circuits are simulated within Agilent Advanced Design Systems environment with good agreement to theoretical prediction. Further the performance of the proposed circuits when operated in a Linear amplification using Nonlinear Components transmitter configuration whereby two-branch amplifiers are driven with constant amplitude conjugate input phase signals is investigated.

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This work presents a systematic analysis on the impact of source-drain engineering using gate

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This paper investigates the control and operation of doubly-fed induction generator (DFIG) and fixed-speed induction generator (FSIG) based wind farms under unbalanced grid conditions. A DFIG system model suitable for analyzing unbalanced operation is developed, and used to assess the impact of an unbalanced supply on DFIG and FSIG operation. Unbalanced voltage at DFIG and FSIG terminals can cause unequal heating on the stator windings, extra mechanical stresses and output power fluctuations. These problems are particularly serious for the FSIG-based wind farm without a power electronic interface to the grid. To improve the stability of a wind energy system containing both DFIG and FSIG based wind farms during network unbalance, a control strategy of unbalanced voltage compensation by the DFIG systems is proposed. The DFIG system compensation ability and the impact of transmission network impedance are illustrated. The simulation results implemented in Matlab/Simulink show that the proposed DFIG control system improves not only its own performance, but also the stability of the FSIG system with the same grid connection point during network unbalance.

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As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCAs unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCAs unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.

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