FPGA montgomery modular multiplication architectures suitable for ECCs over GF(p)

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.

Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

Research-informed design, management and maintenance of infrastructure slopes: development of a multi-scalar approach

The UK’s transport infrastructure is one of the most heavily used in the world. The performance of these networks is critically dependent on the performance of cutting and embankment slopes which make up £20B of the £60B asset value of major highway infrastructure alone. The rail network in particular is also one of the oldest in the world: many of these slopes are suffering high incidents of instability (increasing with time). This paper describes the development of a fundamental understanding of earthwork material and system behaviour, through the systematic integration of research across a range of spatial and temporal scales. Spatially these range from microscopic studies of soil fabric, through elemental materials behaviour to whole slope modelling and monitoring and scaling up to transport networks. Temporally, historical and current weather event sequences are being used to understand and model soil deterioration processes, and climate change scenarios to examine their potential effects on slope performance in futures up to and including the 2080s. The outputs of this research are being mapped onto the different spatial and temporal scales of infrastructure slope asset management to inform the design of new slopes through to changing the way in which investment is made into aging assets. The aim ultimately is to help create a more reliable, cost effective, safer and more resilient transport system.