Decoupled-DFIG fault ride-through strategy for enhanced stability performance during grid faults

This paper proposes a decoupled fault ride-through strategy for a doubly fed induction generator (DFIG) to enhance network stability during grid disturbances. The decoupled operation proposes that a DFIG operates as an induction generator (IG) with the converter unit acting as a reactive power source during a fault condition. The transition power characteristics of the DFIG have been analyzed to derive the capability of the proposed strategy under various system conditions. The optimal crowbar resistance is obtained to exploit the maximum power capability from the DFIG during decoupled operation. The methods have been established to ensure proper coordination between the IG mode and reactive power compensation from the grid-side converter during decoupled operation. The viability and benefits of the proposed strategy are demonstrated using different test network structures and different wind penetration levels. Control performance has been benchmarked against existing grid code standards and commercial wind generator systems, based on the optimal network support required (i.e., voltage or frequency) by the system operator from a wind farm installed at a particular location.

Protection Assessment using Reduced Power System Fault Data

Wavelet transforms provide basis functions for time-frequency analysis and have properties that are particularly useful for the compression of analogue point on wave transient and disturbance power system signals. This paper evaluates the compression properties of the discrete wavelet transform using actual power system data. The results presented in the paper indicate that reduction ratios up to 10:1 with acceptable distortion are achievable. The paper discusses the application of the reduction method for expedient fault analysis and protection assessment.

An ESPRIT-SAA-Based Detection Method for Broken Rotor Bar Fault in Induction Motors

This paper presents a novel detection method for broken rotor bar fault (BRB) in induction motors based on Estimation of Signal Parameters via Rotational Invariance Technique (ESPRIT) and Simulated Annealing Algorithm (SAA). The performance of ESPRIT is tested with simulated stator current signal of an induction motor with BRB. It shows that even with a short-time measurement data, the technique is capable of correctly identifying the frequencies of the BRB characteristic components but with a low accuracy on the amplitudes and initial phases of those components. SAA is then used to determine their amplitudes and initial phases and shows satisfactory results. Finally, experiments on a 3kW, 380V, 50Hz induction motor are conducted to demonstrate the effectiveness of the ESPRIT-SAA-based method in detecting BRB with short-time measurement data. It proves that the proposed method is a promising choice for BRB detection in induction motors operating with small slip and fluctuant load.

Flexible fault ride through strategy for wind farm clusters in power systems with high wind power penetration

This paper investigates a flexible fault ride through strategy for power systems in China with high wind power penetration. The strategy comprises of adaptive fault ride through requirements and maximum power restrictions of the wind farms with weak fault ride through capabilities. The slight faults and moderate faults with high probability are the main defending objective of the strategy. The adaptive fault ride through requirement in the strategy consists of two sub fault ride through requirements, a temporary slight voltage ride through requirement corresponding to a slight fault incident, with a moderate voltage ride through requirement corresponding to a moderate fault. The temporary overloading capability of the wind farm is reflected in both requirements to enhance the capability to defend slight faults and to avoid tripping when the crowbar is disconnected after moderate faults are cleared. For those wind farms that cannot meet the adaptive fault ride through requirement, restrictions are put on the maximum power output. Simulation results show that the flexible fault ride through strategy increases the fault ride through capability of the wind farm clusters and reduces the wind power curtailment during faults.

Thermography-based virtual MPPT scheme for improving PV energy efficiency under partial shading conditions

This paper proposes a new thermography-based maximum power point tracking (MPPT) scheme to address photovoltaic (PV) partial shading faults. Solar power generation utilizes a large number of PV cells connected in series and in parallel in an array, and that are physically distributed across a large field. When a PV module is faulted or partial shading occurs, the PV system sees a nonuniform distribution of generated electrical power and thermal profile, and the generation of multiple maximum power points (MPPs). If left untreated, this reduces the overall power generation and severe faults may propagate, resulting in damage to the system. In this paper, a thermal camera is employed for fault detection and a new MPPT scheme is developed to alter the operating point to match an optimized MPP. Extensive data mining is conducted on the images from the thermal camera in order to locate global MPPs. Based on this, a virtual MPPT is set out to find the global MPP. This can reduce MPPT time and be used to calculate the MPP reference voltage. Finally, the proposed methodology is experimentally implemented and validated by tests on a 600-W PV array. 

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.