A neural network based tool for semi-automatic code transformation

A neural network based tool has been developed to assist in the process of code transformation. The tool offers advice on appropriate transformations within a knowledge-driven, semi-automatic parallelisation environment. We have identified the essential characteristics of codes relevant to loop transformations. A Kohonen network is used to discover structure in the characterised codes thus revealing new knowledge that may be brought to bear on the mapping between codes and transformations or transformation sequences. A transform selector based on this process has been developed and successfully applied to the parallelisation of sequential codes.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs

Continuous MLL-ENL expression is necessary to establish a "Hox Code" and maintain immortalization of hematopoietic progenitor cells

The t[(11;19)(p22;q23)] translocation, which gives rise to the MLL-ENL fusion protein, is commonly found in infant acute leukemias of both the myeloid and lymphoid lineage. To investigate the molecular mechanism of immortalization by MLL-ENL we established a Tet-regulatable system of MLL-ENL expression in primary hematopoietic progenitor cells. Immortalized myeloid cell lines were generated, which are dependent on continued MLL-ENL expression for their survival and proliferation. These cells either terminally differentiate or die when MLL-ENL expression is turned off with doxycycline. The expression profile of all 39 murine Hox genes was analyzed in these cells by real-time quantitative PCR. This analysis showed that loss of MLL-ENL was accompanied by a reduction in the expression of multiple Hoxa genes. By comparing these changes with Hox gene expression in cells induced to differentiate with granulocyte colony-stimulating factor, we show for the first time that reduced Hox gene expression is specific to loss of MLL-ENL and is not a consequence of differentiation. Our data also suggest that the Hox cofactor Meis-2 can substitute for Meis-1 function. Thus, MLL-ENL is required to initiate and maintain immortalization of myeloid progenitors and may contribute to leukemogenesis by aberrantly sustaining the expression of a "Hox code" consisting of Hoxa4 to Hoxa11.

A meta-heuristic approach to parallel code generation

The efficient generation of parallel code for multi-processor environments, is a large and complicated issue. Attempts to address this problem have always resulted in significant input from users. Because of constraints on user knowledge and time, the automation of the process is a promising and practically important research area. In recent years heuristic approaches have been used to capture available knowledge and make it available for the parallelisation process. Here, the introduction of a novel approach of neural network techniques is combined with an expert system technique to enhance the availability of knowledge to aid in the automatic generation of parallel code.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.