Real-time temperature estimation for power MOSFETs considering thermal aging effects

This paper presents a novel real-time power-device temperature estimation method that monitors the power MOSFET's junction temperature shift arising from thermal aging effects and incorporates the updated electrothermal models of power modules into digital controllers. Currently, the real-time estimator is emerging as an important tool for active control of device junction temperature as well as online health monitoring for power electronic systems, but its thermal model fails to address the device's ongoing degradation. Because of a mismatch of coefficients of thermal expansion between layers of power devices, repetitive thermal cycling will cause cracks, voids, and even delamination within the device components, particularly in the solder and thermal grease layers. Consequently, the thermal resistance of power devices will increase, making it possible to use thermal resistance (and junction temperature) as key indicators for condition monitoring and control purposes. In this paper, the predicted device temperature via threshold voltage measurements is compared with the real-time estimated ones, and the difference is attributed to the aging of the device. The thermal models in digital controllers are frequently updated to correct the shift caused by thermal aging effects. Experimental results on three power MOSFETs confirm that the proposed methodologies are effective to incorporate the thermal aging effects in the power-device temperature estimator with good accuracy. The developed adaptive technologies can be applied to other power devices such as IGBTs and SiC MOSFETs, and have significant economic implications. 

Optical Fiber Refractive Index Sensor for Chloride Ion Monitoring

The development of a reflective, gold-coated long-period grating-based sensor for the measurement of chloride ions in solution is discussed. The sensor scheme is based around a long-period fiber grating (LPG)-based Michelson interferometer where the sensor was calibrated and evaluated in the laboratory using sodium chloride solutions, over a wide range of concentrations, from 0.01 to 4.00 M. The grating response creates shifts in the spectral characteristic of the interferometer, formed using the LPG and a reflective surface on the distal end of the fiber, due to the change of refracting index of the solution surrounding it. It was found that the sensitivity of the device could be enhanced over that obtained from a bare fiber by coating the LPG-based interferometer with gold nanoparticles and the results of a cross-comparison of performance were obtained and details discussed. The approach will be explored as a basis to create a portable, low-power device, developed with the potential for installation in concrete structures to determine the ingress of chloride ions, operating through monitoring the refractive index change.

Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

Analysis and Design of Class-E3F and Transmission-Line Class-E3F2 Power Amplifiers

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F2 and transmission-line (TL) Class-E3 F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3 F PA are described. The load networks of the Class-E3 F and TL Class-E 3 F2amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. © 2010 IEEE.

Design technique for mm-wave IC realization of the load network of switched-mode class-EF power amplifier

Analysis and synthesis of the new Class-EF power amplifier (PA) are presented in this paper. The proposed circuit offers means to alleviate some of the major issues faced by existing Class-EF and Class-EF PAs, such as (1) substantial power losses due to parasitic resistance of the large inductor in the Class-EF load network, (2) unpredictable behaviour of practical lumped inductors and capacitors at harmonic frequencies, and (3) deviation from ideal Class-EF operation mode due to detrimental effects of device output inductance at high frequencies. The transmission-line load network of the Class-EF PA topology elaborated in this paper simultaneously satisfies the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Furthermore, an elegant solution using an open and short-circuit stub arrangement is suggested to overcome the problem encountered in the mm-wave IC realizations of the Class-EF PA load network due to lossy quarter-wave line. © 2010 IEICE Institute of Electronics Informati.

Power take-off and damping of an oscillating wave surge converter

The European Union has set a target of 20% for the share of renewable energy sources in gross final energy consumption in 2020. These renewable energy targets are priority objectives for the Europe 2020 strategy for inclusive growth. In line with the European Union renewable energy policies, the Northern Ireland Executive has a target to deliver 40% renewable electricity by 2020. Currently, Northern Ireland imports 98% of the energy it uses in the form of fossil fuels. Locally produced energy and electricity is needed to ensure sustainable development. The aim of this research is to develop part of a strategy for the mechanical power take-off system for a flap type wave energy converter. Aquamarine Power Ltd’s Oyster flap was the device used for simulation and testing purposes. In this paper the state-of-the-art of wave energy converters is reviewed and a 40th scale test model was developed and built.

Human body shadowing in cellular device-to-device communications: channel modeling using the shadowed κ−μ fading model

Using device-to-device communications as an underlay for cellular communications will provide an exciting opportunity to increase network capacity as well as improving spectral efficiency. The unique geometry of device-to-device links, where user equipment is often held or carried at low elevation and in close proximity to the human body, will mean that they are particularly susceptible to shadowing events caused not only by the local environment but also by the user's body. In this paper, the shadowed κ - μ fading model is proposed, which is capable of characterizing shadowed fading in wireless communication channels. In this model, the statistics of the received signal are manifested by the clustering of multipath components. Within each of these clusters, a dominant signal component with arbitrary power may exist. The resultant dominant signal component, which is formed by the phasor addition of these leading contributions, is assumed to follow a Nakagami- m distribution. The probability density function, moments, and the moment-generating function are also derived. The new model is then applied to device-to-device links operating at 868 MHz in an outdoor urban environment. It was found that shadowing of the resultant dominant component can vary significantly depending upon the position of the user equipment relative to the body and the link geometry. Overall, the shadowed κ - μ fading model is shown to provide a good fit to the field data as well as providing a useful insight into the characteristics of the received signal.

Secure D2D Communication in Large-Scale Cognitive Cellular Networks with Wireless Power Transfer

In this paper, we investigate secure device-to-device (D2D) communication in energy harvesting large-scale cognitive cellular networks. The energy constrained D2D transmitter harvests energy from multi-antenna equipped power beacons (PBs), and communicates with the corresponding receiver using the spectrum of the cellular base stations (BSs). We introduce a power transfer model and an information signal model to enable wireless energy harvesting and secure information transmission. In the power transfer model, we propose a new power transfer policy, namely, best power beacon (BPB) power transfer. To characterize the power transfer reliability of the proposed policy, we derive new closed-form expressions for the exact power outage probability and the asymptotic power outage probability with large antenna arrays at PBs. In the information signal model, we present a new comparative framework with two receiver selection schemes: 1) best receiver selection (BRS), and 2) nearest receiver selection (NRS). To assess the secrecy performance, we derive new expressions for the secrecy throughput considering the two receiver selection schemes using the BPB power transfer policies. We show that secrecy performance improves with increasing densities of PBs and D2D receivers because of a larger multiuser diversity gain. A pivotal conclusion is reached that BRS achieves better secrecy performance than NRS but demands more instantaneous feedback and overhead.

Empirical evaluation of multi-device profiling side-channel attacks

Side-channel analysis of cryptographic systems can allow for the recovery of secret information by an adversary even where the underlying algorithms have been shown to be provably secure. This is achieved by exploiting the unintentional leakages inherent in the underlying implementation of the algorithm in software or hardware. Within this field of research, a class of attacks known as profiling attacks, or more specifically as used here template attacks, have been shown to be extremely efficient at extracting secret keys. Template attacks assume a strong adversarial model, in that an attacker has an identical device with which to profile the power consumption of various operations. This can then be used to efficiently attack the target device. Inherent in this assumption is that the power consumption across the devices under test is somewhat similar. This central tenet of the attack is largely unexplored in the literature with the research community generally performing the profiling stage on the same device as being attacked. This is beneficial for evaluation or penetration testing as it is essentially the best case scenario for an attacker where the model built during the profiling stage matches exactly that of the target device, however it is not necessarily a reflection on how the attack will work in reality. In this work, a large scale evaluation of this assumption is performed, comparing the key recovery performance across 20 identical smart-cards when performing a profiling attack.

Long-Term Economic Model for Allocation of FACTS Devices in Restructured Power System Integrated Wind Generation

This study proposes an approach to optimally allocate multiple types of flexible AC transmission system (FACTS) devices in market-based power systems with wind generation. The main objective is to maximise profit by minimising device investment cost, and the system's operating cost considering both normal conditions and possible contingencies. The proposed method accurately evaluates the long-term costs and benefits gained by FACTS devices (FDs) installation to solve a large-scale optimisation problem. The objective implies maximising social welfare as well as minimising compensations paid for generation re-scheduling and load shedding. Many technical operation constraints and uncertainties are included in problem formulation. The overall problem is solved using both particle swarm optimisations for attaining optimal FDs allocation as main problem and optimal power flow as sub-optimisation problem. The effectiveness of the proposed approach is demonstrated on modified IEEE 14-bus test system and IEEE 118-bus test system.

Pre-Processing Power Traces with a Phase-Sensitive Detector

As cryptographic implementations are increasingly subsumed as functional blocks within larger systems on chip, it becomes more difficult to identify the power consumption signatures of cryptographic operations amongst other unrelated processing activities. In addition, at higher clock frequencies, the current decay between successive processing rounds is only partial, making it more difficult to apply existing pattern matching techniques in side-channel analysis. We show however, through the use of a phase-sensitive detector, that power traces can be pre-processed to generate a filtered output which exhibits an enhanced round pattern, enabling the identification of locations on a device where encryption operations are occurring and also assisting with the re-alignment of power traces for side-channel attacks.