Integrating Land Use Planning and Transportation: Policy formulation in the Belfast Metropolitan Area

Much of the interest in sustainable cities relates to the inexorable rise in the demand for car travel and the contribution that certain urban forms and land-use relationships can make to reducing energy consumption. Indeed, this demand is fuelled more by increased spatial separation of homes and workplaces, shops and schools than by any rise in trip making. This paper evaluates recent efforts to integrate land-use planning and transportation policy in the Belfast Metropolitan Area by reviewing the policy formulation process at both a regional and city scale. The paper suggests that considerable progress has been made in integrating these two areas of public policy, both institutionally and conceptually. However, concerns are expressed that the rhetoric of sustainability may prove difficult to translate into implementation, leading to a further dislocation of land-use and transportation.

Integrating Land-use Planning and Transportation in Belfast: A New Policy Agenda for Sustainable Development

Much of the interest in promoting sustainable development in planning for the city-region focuses on the apparently inexorable rise in the demand for car travel and the contribution that certain urban forms and land-use relationships can make to reducing energy consumption. Within this context, policy prescription has increasingly favoured a compact city approach with increasing urban residential densities to address the physical separation of daily activities and the resultant dependency on the private car. This paper aims to outline and evaluate recent efforts to integrate land use and transport policy in the Belfast Metropolitan Area in Northern Ireland. Although considerable progress has been made, this paper underlines the extent of existing car dependency in the metropolitan area and prevailing negative attitudes to public transport, and argues that although there is a rhetorical support for the principles of sustainability and the practice of land-use/transportation integration, this is combined with a selective reluctance to embrace local changes in residential environment or in lifestyle preferences which might facilitate such principles.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.