Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Intellectual Property management in publicly funded R&D centres—A comparison of university-based and company-based research centres

Recent thinking on open innovation and the knowledge-based economy have stressed the importance of external knowledge sources in stimulating innovation. Policy-makers have recognised this, establishing publicly funded Centres of R&D Excellence with the objective of stimulating industry–science links and localised innovation spillovers. Here, we examine the contrasting IP management practices of a group of 18 university- and company-based R&D centres supported by the same regional programme. Our analysis covers all but one of the Centres supported by the programme and suggests marked contrasts between the IP strategies of the university-based and company-based centres. This suggests the potential for very different types of knowledge spillovers from publicly funded R&D centres based in different types of organisations, and a range of alternative policy approaches to the future funding of R&D centres depending on policy-makers’ objectives.

Intellectual Property and the EU’s Deep Trade Agenda

The EU is considered to be one of the main proponents of what has been called the deep trade agenda—that is, the push for further trade liberalization with an emphasis on the removal of domestic non-tariff regulatory measures affecting trade, as opposed to the traditional focus on the removal of trade barriers at borders. As negotiations on the Doha Development Round have stalled, the EU has attempted to achieve these aims by entering into comprehensive free trade agreements (FTAs) that are not only limited exclusively to tariffs but also extend to non-tariff barriers, including services, intellectual property rights (IPRs), competition, and investment. These FTAs place great emphasis on regulatory convergence as a means to secure greater market openings. The paper examines the EU's current external trade policy in the area of IP, particularly its attempts to promote its own regulatory model for the protection of IP rights through trade agreements. By looking at the IP enforcement provisions of such agreements, the article also examines how the divisive issues that are currently hindering the progress of negotiations at WTO level, including the demands from developing countries to maintain a degree of autonomy in the area of IP regulation as well as the need to balance IP protection with human rights protection, are being dealt with in recent EU FTAs.

BOOK: Property Rights and Human Rights in a Global Context

Property as a human rights concern is manifested through its incorporation in international instruments and as a subject of the law through property-related cases considered by international human rights organs. Yet, for the most part, the relationship between property and human rights has been discussed in rather superficial terms, lacking a clear substantive connection or common language. That said, the currents of globalisation have witnessed a new era of interrelation between these two areas of the law, including the emergence of international intellectual property law and the recognition of indigenous claims, which, in fundamental ways, speak to an engagement with human rights law.

This collection starts the conversation between human rights lawyers and property lawyers and explores analytical approaches to the increasing relationship between property and human rights in a global context. The chapters engage with key theoretical and policy debates and range across three main themes: the re-evaluation of the public/private divide in the law; the tensions between the market and social justice in development and the balance between the rights of individuals and those of communities. The chapters adopt a global, comparative perspective and engage in case studies from countries including India, Philippines, Brazil, the United States, the United Kingdom and includes various regions of Africa and Europe.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.