Physical modelling of millimetre wave signal reflection from forward biased PIN diodes

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the i-region. The study is conducted using device level simulation of SOI and bulk PIN diodes and reflection modelling based on the Drude conduction model. We examined five diode lengths (60–140 µm) and seven diode thicknesses (4–100 µm). Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100 GHz operation. It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100 GHz. Thinner devices consume less DC power, but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes.

The electrical characterization and response to hydrogen of Schottky diodes with a resistive metal electrode—rectifying an oversight in Schottky diode investigation

Schottky-barrier structures with a resistive metal electrode are examined using the 4-point probe method where the probes are connected to the metal electrode only. The observation of a significant decrease in resistance with increasing temperature (over a range of similar to 100 K) in the diode resistance-temperature (R(D)-T) characteristic is considered due to charge carrier confinement to the metal electrode at low temperature (high resistance), with the semiconductor progressively opening up as a parallel current carrying channel (low resistance) with increasing temperature due to increasing thermionic emission across the barrier. A simple model is constructed, based on thermionic emission at quasi-zero bias, that generates good fits to the experimental data. The negative differential resistance (NDR) region in the R(D)-T characteristic is a general effect and is demonstrated across a broad temperature range for a variety of Schottky structures grown on Si-, GaAs- and InP-substrates. In addition the NDR effect is harnessed in micro-scaled Pd/n-InP devices for the detection of low levels of hydrogen in an ambient atmosphere of nitrogen.

Hybrid FIB milling strategy for the fabrication of plasmonic nanostructures on semiconductor substrates

The optical properties of plasmonic semiconductor devices fabricated by focused ion beam (FIB) milling deteriorate because of the amorphisation of the semiconductor substrate. This study explores the effects of combining traditional 30 kV FIB milling with 5 kV FIB patterning to minimise the semiconductor damage and at the same time maintain high spatial resolution. The use of reduced acceleration voltages is shown to reduce the damage from higher energy ions on the example of fabrication of plasmonic crystals on semiconductor substrates leading to 7-fold increase in transmission. This effect is important for focused-ion beam fabrication of plasmonic structures integrated with photodetectors, light-emitting diodes and semiconductor lasers.

PHOTOSIGNAL ENHANCEMENT IN AL-GAAS DIODES DUE TO SURFACE-PLASMONS AND GUIDED-WAVE MODES

Light of wavelength 632.8 nm and p-polarization is incident on a prism-air gap (varied from 0.7 to 7 mum)-Al-GaAs arrangement. Both the photosignal generated by the Schottky diode and the reflectance are measured as a function of the internal angle of incidence in the prism. There is significant, well-defined enhancement of the photosignal, up to a factor of approximately 7.5, associated with two different types of enhanced absorption modes. For air gaps <1.5 mum there is photosignal enhancement due to an enhanced absorption feature (reflectance dip) that occurs at an angle of incidence just above critical angle in the prism; this feature corresponds to the excitation of a surface plasmon polariton at the Al-air interface. For air gaps > 1 mum there are between one and ten photoresponse peaks at input angles less than the critical angle. The corresponding enhanced absorption features are due to leaky guided wave modes set up in the air gap.

ANALYSIS OF SURFACE-PLASMON POLARITON ENHANCEMENT IN PHOTODETECTION BY AL-GAAS SCHOTTKY DIODES

The surface plasmon polariton mediated photoresponse from Al-GaAs diodes is examined in a prism-air gap-diode configuration as a function of both the wavelength of the incident light and thickness of the Al electrode. The experimental data shows a pronounced dip in reflectance as a function of internal angle of incidence in the prism, due to the excitation of the surface plasmon polariton at the Al-air interface, and a corresponding peak in device photosignal. Careful modelling of reflectance and quantum efficiency data shows that the bulk of the signal is generated by light which is re-radiated from this surface mode into the semiconductor substrate where it is absorbed by the creation of electron-hole pairs in the depletion region. This holds for all the wavelengths used here (all are shorter than the GaAs absorption edge) and across the thickness range of the Al electrodes (20-50 nm). Quantum efficiencies in the range 0.5-22% and enhancement factors of typically 7.5 were recorded in this investigation.

Modeling and simulation of bulk gallium nitride power semiconductor devices

Bulk gallium nitride (GaN) power semiconductor devices are gaining significant interest in recent years, creating the need for technology computer aided design (TCAD) simulation to accurately model and optimize these devices. This paper comprehensively reviews and compares different GaN physical models and model parameters in the literature, and discusses the appropriate selection of these models and parameters for TCAD simulation. 2-D drift-diffusion semi-classical simulation is carried out for 2.6 kV and 3.7 kV bulk GaN vertical PN diodes. The simulated forward current-voltage and reverse breakdown characteristics are in good agreement with the measurement data even over a wide temperature range.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.

Surface plasmons in layered structures with semiconductor and metallic films

The complete spectrum of eigenwaves including surface plasmon polaritons (SPP), dynamic (bulk) and complex waves in the layered structures containing semiconductor and metallic films has been explored. The effects of loss, geometry and the parameters of dielectric layers on the eigenmode spectrum and, particularly, on the SPP modes have been analysed using both the asymptotic and rigorous numerical solutions of the full-wave dispersion equation. The field and Poynting vector distributions have been examined to identify the modes and elucidate their properties. It has been shown that losses and dispersion of permittivity qualitatively alter the spectral content and the eigenwave properties. The SPP counter-directional power fluxes in the film and surrounding dielectrics have been attributed to vortices of power flow, which are responsible for the distinctive features of SPP modes. It has been demonstrated for the first time that the maximal attainable slow-wave factor of the SPP modes guided by thin Au films at optical frequencies is capped not by losses but the frequency dispersion of the actual Au permittivity. © 2009 EDP Sciences.