Characterization of a high-density, direct-current reflex discharge plasma source operating in Ar and N-2

The characterization of a direct current, low-pressure, and high-density reflex discharge plasma source operating in argon and in nitrogen, over a range of pressures 1.0-10(-2) mbar, discharge currents 20-200 mA, and magnetic fields 0-120 G, and its parametric characterization is presented. Both external parameters, such as the breakdown potential and the discharge voltage-current characteristic, and internal parameters, like the charge carrier's temperature and density, plasma potential, floating potential, and electron energy distribution function, were measured. The electron energy distribution functions are bi-Maxwellian, but some structure is observed in these functions in nitrogen plasmas. There is experimental evidence for the existence of three groups of electrons within this reflex discharge plasma. Due to the enhanced hollow cathode effect by the magnetic trapping of electrons, the density of the cold group of electrons is as high as 10(18) m(-3), and the temperature is as low as a few tenths of an electron volt. The bulk plasma density scales with the dissipated power. Another important feature of this reflex plasma source is its high degree of uniformity, while the discharge bulk region is free of electric field. (C) 2002 American Institute of Physics.

High-density and low electron temperature direct current reflex plasma source

A new type of direct current, high-density, and low electron temperature reflex plasma source, obtained as a hybrid between a modified hollow-cathode discharge and a Penning ionization gauge discharge is presented. The plasma source was tested in argon, nitrogen, and oxygen over a range pressure of 1.0-10(-3) mbar, discharge currents 20-200 mA, and magnetic field 0-120 Gauss. Both external parameters, such as breakdown potential and the discharge voltage-current characteristic, and its internal parameters, like the electron energy distribution function, electron and ion densities, and electron temperature, were measured. Due to the enhanced hollow-cathode effect by the magnetic trapping of electrons, the density of the bulk plasma is as high as 10(18) m(-3), and the electron temperature is as low as a few tenths of electron volts. The plasma density scales with the dissipated power. Another important feature of this reflex plasma source is its high degree of uniformity, while the discharge bulk region is free of an electric field. (C) 2004 American Institute of Physics.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Investigation of an electron string ion source with field emission cathode

The string mode of operation for an electron beam ion source uses axially oscillating electrons in order to reduce power consumption, also simplifying the construction by omitting the collector with cooling requirements and has been called electron string ion source (ESIS). We have started a project (supported by INTAS and GSI) to use Schottky field emitting cathode tips for generating the electron string. The emission from these specially conditioned tips is higher by orders of magnitude than the focused Brillouin current density at magnetic fields of some Tesla and electron energies of some keV. This may avoid the observed instabilities in the transition from axially oscillating electrons to the string state of the electron plasma, opening a much wider field of possible operating parameters for an ESIS. Besides the presentation of the basic features, we emphasize in this paper a method to avoid damaging of the field, emission tip by backstreaming ions. (C) 2008 American Institute of Physics.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Approaches to the Implementation of the Water Framework Directive: Targeting Mitigation Measures at Critical Source Areas of Diffuse Phosphorus in Irish Catchments

The Water Framework Directive (WFD) has initiated a shift towards a targeted approach to implementation through its focus on river basin districts as management units and the natural ecological characteristics of waterbodies. Due to its role in eutrophication, phosphorus (P) has received considerable attention, resulting in a significant body of research, which now forms the evidence base for the programme of measures (POMs) adopted in WFD River Basin Management Plans (RBMP). Targeting POMs at critical sources areas (CSAs) of P could significantly improve environmental efficiency and cost effectiveness of proposed mitigation strategies. This paper summarises the progress made towards targeting mitigation measures at CSAs in Irish catchments. A review of current research highlights that knowledge related to P export at field scale is relatively comprehensive however; the availability of site-specific data and tools limits widespread identification of CSA at this scale. Increasing complexity of hydrological processes at larger scales limits accurate identification of CSA at catchment scale. Implementation of a tiered approach, using catchment scale tools in conjunction with field-by-field surveys could decrease uncertainty and provide a more practical and cost effective method of delineating CSA in a range of catchments. Despite scientific and practical uncertainties, development of a tiered CSA-based approach to assist in the development of supplementary measures would provide a means of developing catchment-specific and cost-effective programmes of measures for diffuse P. The paper presents a conceptual framework for such an approach, which would have particular relevance for the development of supplementary measures in High Status Waterbodies (HSW). The cost and resources necessary for implementation are justified based on HSWs’ value as undisturbed reference condition ecosystems.

Plasma parameter characterization of a reflex plasma source operating in oxygen

A reflex discharge plasma, obtained as a hybrid between a Penning discharge plasma (PDP) and a hollow-cathode discharge (HCD) plasma, is analysed as a possible direction-current, high-density plasma source. The experiment is run in oxygen at pressures of 10 mTorr and 1 mTorr, and for discharge currents of 100 to 200 mA. Although the gas pressure is considerably lower than those used in HCDs, the hollow-cathode effect (HCE) occurs for current levels higher than 100 mA and leads to plasma densities comparable with those obtained using inductive plasma sources. The presence of a constant magnetic field leads to the enhancement of electron emission from cathodes under ion bombardment, and to the decreasing of the ion loss by diffusion to the wall.

Adaptive backstepping droop controller design for multi-terminal high-voltage direct current systems

Wind power is one of the most developed renewable energy resources worldwide. To integrate offshore wind farms to onshore grids, the high-voltage direct current (HVDC) transmission cables interfaced with voltage source converters (VSCs) are considered to be a better solution than conventional approaches. Proper DC voltage indicates successive power transfer. To connect more than one onshore grid, the DC voltage droop control is one of the most popular methods to share the control burden between different terminals. However, the challenges are that small droop gains will cause voltage deviations, while higher droop gain settings will cause large oscillations. This study aims to enhance the performance of the traditional droop controller by considering the DC cable dynamics. Based on the backstepping control concept, DC cables are modelled with a series of capacitors and inductors. The final droop control law is deduced step-by-step from the original remote side. At each step the control error from the previous step is considered. Simulation results show that both the voltage deviations and oscillations can be effectively reduced using the proposed method. Further, power sharing between different terminals can be effectively simplified such that it correlates linearly with the droop gains, thus enabling simple yet accurate system operation and control.