Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers

As ubiquitous computing becomes a reality, sensitive information is increasingly processed and transmitted by smart cards, mobile devices and various types of embedded systems. This has led to the requirement of a new class of lightweight cryptographic algorithm to ensure security in these resource constrained environments. The International Organization for Standardization (ISO) has recently standardised two low-cost block ciphers for this purpose, Clefia and Present. In this paper we provide the first comprehensive hardware architecture comparison between these ciphers, as well as a comparison with the current National Institute of Standards and Technology (NIST) standard, the Advanced Encryption Standard.

On the Security of Balanced Encoding Countermeasures

Most cryptographic devices should inevitably have a resistance against the threat of side channel attacks. For this, masking and hiding schemes have been proposed since 1999. The security validation of these countermeasures is an ongoing research topic, as a wider range of new and existing attack techniques are tested against these countermeasures. This paper examines the side channel security of the balanced encoding countermeasure, whose aim is to process the secret key-related data under a constant Hamming weight and/or Hamming distance leakage. Unlike previous works, we assume that the leakage model coefficients conform to a normal distribution, producing a model with closer fidelity to real-world implementations. We perform analysis on the balanced encoded PRINCE block cipher with simulated leakage model and also an implementation on an AVR board. We consider both standard correlation power analysis (CPA) and bit-wise CPA. We confirm the resistance of the countermeasure against standard CPA, however, we find with a bit-wise CPA that we can reveal the key with only a few thousands traces.

Polystyrene and asphaltene micelles within blends with a bitumen of an SBS block copolymer and styrene and butadiene homopolymers

Using fluorescence microscopy, DSC and DMTA we have explored blends of a bitumen with a styrene-butadiene-styrene (SBS) block copolymer, and with blends of the bitumen with SBS and one or two homopolymers - a polystyrene and a poly(cis-butadiene). The SBS polymer was progressively replaced with quantities of the homopolymers both together in the proportions found in the block copolymer and then by each homopolymer separately. At low temperatures the blends are all softer than the bitumen itself, so the polymers plasticise the bitumen-rich phase, and above 50°C the blends' stiffness (E') falls below a plateau only when a critical proportion of the block copolymer has been replaced with the two homopolymers: this supports the idea of an extensive network created by the polystyrene-rich spherical microphases that is effective even when the polystyrene microphases have melted. In one polymer blend the stiffness rose as the temperature was raised above 100°C, suggesting the development of a mesophase based upon polybutadiene plus asphaltenes, in another E' was enhanced and E" remained constant as the temperature rose above 70°C, perhaps for a similar reason; in some loss process appeared and the stiffness fell as temperature rose; but in others a good part of the SBS was replaced by either polystyrene or polybutadiene without changing the appearance of a rubbery plateau, that is, without a diminution of the mechanical properties of the soft matter.

A VLSI Architecture for Variable Block Size Video Motion Estimation

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.

WLAN Security Processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures. © 2006 IEEE.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Org 25969 (sugammadex), a selective relaxant binding agent for antagonism of prolonged rocuronium-induced neuromuscular block

Background. Org 25969 is a cyclodextrin compound designed to reverse a rocuronium-induced neuromuscular block. The aim of this study was to explore the efficacy, dose-response relation and safety of Org 25969 for reversal of a prolonged rocuronium-induced neuromuscular block. Methods. Thirty anaesthetised adult patients received rocuronium 0.6mg kg as an initial dose followed by increments to maintain a deep block at level of

Postoperative residuial block after intermediate-acting neuromuscular blocking drugs

Summary The frequency and duration of postoperative residual neuromuscular block on arrival of 150 patients in the recovery ward following the use of vecuronium (n = 50), atracurium (n = 50) and rocuronium (n = 50) were recorded. Residual block was defined as a train-of-four ratio of 0.8 after arrival in the recovery ward were 9.2 [1-61], 6.9 [1-24] and 14.7 [1.5-83] min for the vecuronium, atracurium and rocuronium, respectively. None of the 10 patients who did not receive neuromuscular blocking drugs had train-of-four ratios

Neostigmine antagonism of rocuronium block during anesthesia with sevoflurane, isoflurane or propofol

Purpose: To examine the influence of continuing administration of sevoflurane or isoflurane during reversal of rocuronium induced neuromuscular block with neostigmine. Methods: One hundred and twenty patients, divided into three equal groups, were randomly allocated to maintenance of anesthesia with sevoflurane, isoflurane or propofol. Neuromuscular block was induced with rocuronium and monitored using train-of-four (TOF) stimulation of the ulnar nerve and recording the force of contraction of the adductor pollicis muscle. Neostigmine was administered when the first response in TOF had recovered to 25%. At this time the volatile agent administration was stopped or propofol dosage reduced in half the patients in each group (n = 20 in each group). The times to attain TOF ratio of 0.8, and the number of patients attaining this end point within 15 min were recorded. Results: The times (mean ± SD) to recovery of the TOF ratio to 0.8 were 12.0 ± 5.5 and 6.8 ± 2.3 min in the sevoflurane continued and sevoflurane stopped groups, 9.0 ± 8.3 and 5.5 ± 3.0 min in the isoflurane continued and isoflurane stopped groups, and 5.2 ± 2.8 and 4.7 ±1.5 min in the propofol continued and propofol stopped groups (P <0.5- 01). Only 9 and 15 patients in the sevoflurane and isoflurane continued groups respectively had attained a TOF ratio of 0.8 within 15 min (P <0.001 for sevoflurane). Conclusions: The continued administration of sevoflurane, and to a smaller extent isoflurane, results in delay in attaining adequate antagonism of rocuronium induced neuromuscular block.

An unusual delayed complication of inferior alveolar nerve block

Systemic and localised complications after administration of local anaesthetic for dental procedures are well recognised. We present two cases of patients with trismus and sensory deficit that arose during resolution of trismus as a delayed complication of inferior alveolar nerve block.