Drivetrain Effects on Small Engine Performance

Presented is a study that expands the body of knowledge on the effect of in-cycle speed fluctuations on performance of small engines. It uses the methods developed previously by Callahan, et al. (1) to examine a variety of two-stroke engines and one four-stroke engine. The two-stroke engines were: a high performance single-cylinder, a low performance single-cylinder, a high performance multi-cylinder, and a medium performance multi-cylinder. The four-stroke engine was a high performance single-cylinder unit. Each engine was modeled in Virtual Engines, which is a fully detailed one-dimensional thermodynamic engine simulator. Measured or predicted in-cycle speed data were input into the engine models. Predicted performance changes due to drivetrain effects are shown in each case, and conclusions are drawn from those results. The simulations for the high performance single-cylinder two-stroke engine predicted significant in-cycle crankshaft speed fluctuation amplitudes and significant changes in performance when the fluctuations were input into the engine model. This was validated experimentally on a firing test engine based on a Yamaha YZ250. The four-stroke engine showed significant changes in predicted performance compared to the prediction with zero speed fluctuation assumed in the model. Measured speed fluctuations from a firing Yamaha YZ400F engine were applied to the simulation in addition to data from a simple free mass model. Both methods predicted similar fluctuation profiles and changes in performance. It is shown that the gear reduction between the crankshaft and clutch allowed for this similar behavior. The multi-cylinder, high performance two-stroke engine also showed significant changes in performance, in this case depending on the firing configuration. The low output two-stroke engine simulation showed only a negligible change in performance in spite of high amplitude speed fluctuations. This was due to its flat torque versus speed characteristic. The medium performance multi-cylinder two-stroke engine also showed only a negligible change in performance, in this case due to a relatively high inertia rotating assembly and multiple cylinder firing events within the revolution. These smoothed the net torque pulsations and reduced the amplitude of the speed fluctuation itself.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Real-valued fixed-complexity sphere decoder for high dimensional QAM-MIMO systems

The development of high performance, low computational complexity detection algorithms is a key challenge for real-time Multiple-Input Multiple-Output (MIMO) communication system design. The Fixed-Complexity Sphere Decoder (FSD) algorithm is one of the most promising approaches, enabling quasi-ML decoding accuracy and high performance implementation due to its deterministic, highly parallel structure. However, it suffers from exponential growth in computational complexity as the number of MIMO transmit antennas increases, critically limiting its scalability to larger MIMO system topologies. In this paper, we present a solution to this problem by applying a novel cutting protocol to the decoding tree of a real-valued FSD algorithm. The new Real-valued Fixed-Complexity Sphere Decoder (RFSD) algorithm derived achieves similar quasi-ML decoding performance as FSD, but with an average 70% reduction in computational complexity, as we demonstrate from both theoretical and implementation perspectives for Quadrature Amplitude Modulation (QAM)-MIMO systems.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.

High Strength Thermoplastic Bonding for Multi-channel, Multi-layer Lab-on-Chip Devices for Ocean and Environmental applications

A solvent-vapour thermoplastic bonding process is reported which provides high strength bonding of PMMA over a large area for multi-channel and multi-layer microfluidic devices with shallow high resolution channel features. The bond process utilises a low temperature vacuum thermal fusion step with prior exposure of the substrate to chloroform (CHCl3) vapour to reduce bond temperature to below the PMMA glass transition temperature. Peak tensile and shear bond strengths greater than 3 MPa were achieved for a typical channel depth reduction of 25 µm. The device-equivalent bond performance was evaluated for multiple layers and high resolution channel features using double-side and single-side exposure of the bonding pieces. A single-sided exposure process was achieved which is suited to multi-layer bonding with channel alignment at the expense of greater depth loss and a reduction in peak bond strength. However, leak and burst tests demonstrate bond integrity up to at least 10 bar channel pressure over the full substrate area of 100 mm x 100 mm. The inclusion of metal tracks within the bond resulted in no loss of performance. The vertical wall integrity between channels was found to be compromised by solvent permeation for wall thicknesses of 100 µm which has implications for high resolution serpentine structures. Bond strength is reduced considerably for multi-layer patterned substrates where features on each layer are not aligned, despite the presence of an intermediate blank substrate. Overall a high performance bond process has been developed that has the potential to meet the stringent specifications for lab-on-chip deployment in harsh environmental conditions for applications such as deep ocean profiling.

Facile synthesis of nanocrystalline LiFePO4/graphene composite as cathode material for high power lithium ion batteries

We describe a simple strategy, which is based on the idea of space confinement, for the synthesis of carbon coating on LiFePO₄ nanoparticles/graphene nanosheets composites in a water-in-oil emulsion system. The prepared composite displayed high performance as a cathode material for lithium-ion battery, such as high reversible lithium storage capacity (158 mA h g^-1 after 100 cycles), high coulombic efficiency (over 97%), excellent cycling stability and high rate capability (as high as 83 mA h g ^-1 at 60 C). Very significantly, the preparation method employed can be easily adapted and be extended as a general approach to sophisticated compositions and structures for the preparation of highly dispersed nanosized structure on graphene. 

Facile Synthesis of Anatase TiO2 Quantum-Dot/Graphene-Nanosheet Composites with Enhanced Electrochemical Performance for Lithium-Ion Batteries

A facile method to synthesize well-dispersed TiO₂ quantum dots on graphene nanosheets (TiO₂-QDs/GNs) in a water-in-oil (W/O) emulsion system is reported. The TiO₂/graphene composites display high performance as an anode material for lithium-ion batteries (LIBs), such as having high reversible lithium storage capacity, high Coulombic efficiency, excellent cycling stability, and high rate capability. The excellent electrochemical performance and special structure of the composites thus offer a way to prepare novel graphene-based electrode materials for high-energy-density and high-power LIBs. 

Multi-Tenant Virtual GPUs for Optimising Performance of a Financial Risk Application

Graphics Processing Units (GPUs) are becoming popular accelerators in modern High-Performance Computing (HPC) clusters. Installing GPUs on each node of the cluster is not efficient resulting in high costs and power consumption as well as underutilisation of the accelerator. The research reported in this paper is motivated towards the use of few physical GPUs by providing cluster nodes access to remote GPUs on-demand for a financial risk application. We hypothesise that sharing GPUs between several nodes, referred to as multi-tenancy, reduces the execution time and energy consumed by an application. Two data transfer modes between the CPU and the GPUs, namely concurrent and sequential, are explored. The key result from the experiments is that multi-tenancy with few physical GPUs using sequential data transfers lowers the execution time and the energy consumed, thereby improving the overall performance of the application.