Circulating and synovial antibody profiling of juvenile arthritis patients by nucleic acid programmable protein arrays.

Introduction Juvenile idiopathic arthritis (JIA) is a heterogeneous disease characterized by chronic joint inflammation of unknown cause in children. JIA is an autoimmune disease and small numbers of auto-antibodies have been reported in JIA patients. The identification of antibody markers could improve the existing clinical management of patients. Methods A pilot study was performed on the application of a high-throughput platform, nucleic acid programmable protein arrays (NAPPA), to assess the levels of antibodies present in the systemic circulation and synovial joint of a small cohort of juvenile arthritis patients. Plasma and synovial fluid from ten JIA patients was screened for antibodies against 768 proteins on NAPPA. Results Quantitative reproducibility of NAPPA was demonstrated with >0.95 intra- and inter- array correlations. A strong correlation was also observed for the levels of antibodies between plasma and synovial fluid across the study cohort (r=0.96). Differences in the levels of 18 antibodies were revealed between sample types across all patients. Patients were segregated into two clinical subtypes with distinct antibody signatures by unsupervised hierarchical cluster analysis. Conclusions NAPPA provides a high-throughput quantitatively reproducible platform to screen for disease specific autoantibodies at the proteome level on a microscope slide. The strong correlation between the circulating antibody levels and those of the inflamed joint represents a novel finding and provides confidence to use plasma for discovery of autoantibodies in JIA, thus circumventing the challenges associated with joint aspiration. We expect that autoantibody profiling of JIA patients on NAPPA could yield antibody markers that can act as criteria to stratify patients, predict outcomes and understand disease etiology at the molecular level.

Field-programmable true random number generator

True random number generation is crucial in hardware security applications. Proposed is a voltage-controlled true random number generator that is inherently field-programmable. This facilitates increased entropy as a randomness source because there is more than one configuration state which lends itself to more compact and low-power architectures. It is evaluated through electrical characterisation and statistically through industry-standard randomness tests. To the best of the author's knowledge, it is one of the most efficient designs to date with respect to hardware design metrics.

Embedded C programming: a practical course introducing programmable microprocessors

This paper presents a new laboratory-based module for embedded systems teaching, which addresses the current lack of consideration for the link between hardware development, software implementation, course content and student evaluation in a laboratory environment. The course introduces second year undergraduate students to the interface between hardware and software and the programming of embedded devices; in this case, the PIC (originally peripheral interface controller, later rebranded programmable intelligent computer) microcontroller. A hardware development board designed for use in the laboratories of this module is presented. Through hands on laboratory experience, students are encouraged to engage with practical problem-solving exercises and develop programming skills across a broad range of scenarios.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Amplitude-modulation characteristics of power-combining Class-E amplifier with finite choke

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio. © 2011 The Institution of Engineering and Technology.