135 resultados para academic programming


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Performance evaluation of parallel software and architectural exploration of innovative hardware support face a common challenge with emerging manycore platforms: they are limited by the slow running time and the low accuracy of software simulators. Manycore FPGA prototypes are difficult to build, but they offer great rewards. Software running on such prototypes runs orders of magnitude faster than current simulators. Moreover, researchers gain significant architectural insight during the modeling process. We use the Formic FPGA prototyping board [1], which specifically targets scalable and cost-efficient multi-board prototyping, to build and test a 64-board model of a 512-core, MicroBlaze-based, non-coherent hardware prototype with a full network-on-chip in a 3D-mesh topology. We expand the hardware architecture to include the ARM Versatile Express platforms and build a 520-core heterogeneous prototype of 8 Cortex-A9 cores and 512 MicroBlaze cores. We then develop an MPI library for the prototype and evaluate it extensively using several bare-metal and MPI benchmarks. We find that our processor prototype is highly scalable, models faithfully single-chip multicore architectures, and is a very efficient platform for parallel programming research, being 50,000 times faster than software simulation.

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This paper considers the potential for improving the reputation of the Irish accountancy profession by exploring undergraduate accounting students’ intolerance of academic cheating as a predictor of future attitudes to unethical workplace practices. The study reports that females are significantly more intolerant of cheating than males. Further, with regard to ethical ideology, idealism was found to have a significant positive association with intolerance of cheating while relativism reported no association. It is anticipated that the growing admission of women to professional accountancy membership together with educational intervention to increase idealism may improve ethical attitudes and help restore the profession's reputation.

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This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demon- strates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.

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A formal specification of a complex programming language statement is presented. The subject matter was selected as being typical of the kind confronting a small software house. It is shown that formal specification notations may be applied, with benefit, to 'messy' problems. Emphasis is placed upon producing a specification which is readable by, and useful to a reader not familiar with formal notations.

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Structured parallel programming is recognised as a viable and effective means of tackling parallel programming problems. Recently, a set of simple and powerful parallel building blocks RISC pb2l) has been proposed to support modelling and implementation of parallel frameworks. In this work we demonstrate how that same parallel building block set may be used to model both general purpose parallel programming abstractions, not usually listed in classical skeleton sets, and more specialized domain specific parallel patterns. We show how an implementation of RISC pb2 l can be realised via the FastFlow framework and present experimental evidence of the feasibility and efficiency of the approach.

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Objective. To ascertain goal orientations of pharmacy students and establish whether associations exist between academic performance, gender, or year of study. Methods. Goal orientations were assessed using a validated questionnaire. Respondents were categorized as high or low performers based on university grades. Associations and statistical significance were ascertained using parametric and nonparametric tests and linear regression, as appropriate. Results. A response rate of 60.7% was obtained. High performers were more likely to be female than male. The highest mean score was for mastery approach; the lowest for work avoidance. The mean score for work avoidance was significantly greater for low performers than for high performers and for males than for females. First-year students were most likely to have top scores in mastery and performance approaches. Conclusion. It is encouraging that the highest mean score was for mastery approach orientation, as goal orientation may play a role in academic performance of pharmacy students.