Systolic two-port adaptor for high performance wave digital filtering

The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.

Synthesizable high performance adaptive equaliser and viterbi decoder for the class-IV PRML channel

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

A research-based approach to exploring the adoption of novel UK-based concrete test methods in Chinese construction sector

As part of a UK-China science bridge project - a UK government funded initiative linking leading universities and businesses in selective partnering countries in 2009 a collaborative research programme was initiated between Queen's University and the Research Institute of High Performance Concrete (part of the Central Research Institute of Building and Construction) in Beijing.

For further details email b.magee@ulster.ac.uk

Hydrophilic Interaction Ultra-High Performance Liquid Chromatography Coupled with Triple-Quadrupole Mass Spectrometry for Determination of Nucleosides and Nucleobases in Animal Horns

Traditional Chinese Medicines (TCMs) derived from animal horns are one of the most important types of Chinese medicine. In the present study, a fast and sensitive analytical method was established for qualitative and quantitative determination of 14 nucleosides and nucleobases in animal horns using hydrophilic interaction ultra-high performance liquid chromatography coupled with triple-quadruple tandem mass spectrometry (HILIC-UPLC-QQQ-MS/MS) in selective reaction monitoring (SRM) mode. The method was optimized and validated, and showed good linearity, precision, repeatability, and accuracy. The method was successfully used to determine contents of the 14 nucleosides and nucleobases in 25 animal horn samples. Hierarchical clustering analysis (HCA) and principal component analysis (PCA) were performed and the 25 samples were thereby divided into two groups, which agreed with taxonomy. The method may enable quick and effective search of substitutes for precious horns.

A high performance IIR digital filter chip

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.

Surface modification of LiV3O8 nanosheets via layer-by-layer self-assembly for high-performance rechargeable lithium batteries

In this work, an economical route based on hydrothermal and layer-by-layer (LBL) self-assembly processes has been developed to synthesize unique Al ₂O₃-modified LiV₃O₈ nanosheets, comprising a core of LiV₃O₈ nanosheets and a thin Al ₂O₃ nanolayer. The thickness of the Al₂O ₃ nanolayer can be tuned by altering the LBL cycles. When evaluated for their lithium-storage properties, the 1 LBL Al₂O ₃-modified LiV₃O₈ nanosheets exhibit a high discharge capacity of 191 mA h g^-1 at 300 mA g^-1 (1C) over 200 cycles and excellent rate capability, demonstrating that enhanced physical and/or chemical properties can be achieved through proper surface modification. © 2014 Elsevier B.V. All rights reserved.