Plasma Ionization in Low-Pressure Radio-Frequency Discharges. Part I: Optical Measurements

The electron dynamics in the low-pressure operation regime ($«$ 5 Pa) of a neon capacitively coupled plasma is investigated using phase-resolved optical emission spectroscopy. Plasma ionization and sustainment mechanisms are governed by the expanding and contracting sheath and complex wave–particle interactions. Electrons are energized through the advancing and retreating electric field of the RF sheath. The associated interaction of energetic sheath electrons with thermal bulk plasma electrons drives a two-stream instability also dissipating power in the plasma.

Plasma Ionization in Low-Pressure Radio-Frequency Discharges—Part II: Particle-in-Cell Simulation

Plasma ionization in the low-pressure operation regime ( $«$ 5 Pa) of RF capacitively coupled plasmas (CCPs) is governed by a complex interplay of various mechanisms, such as field reversal, sheath expansion, and wave–particle interactions. In a previous paper, it was shown that experimental observations in a hydrogen CCP operated at 13.56 MHz are qualitatively well described in a 1-D symmetrical particle-in-cell (PIC) simulation. In this paper, a spherical asymmetrical PIC simulation that is closer to the conditions of the highly asymmetrical experimental device is used to simulate a low-pressure neon CCP operated at 2 MHz. The results show a similar behavior, with pronounced ionization through field reversal, sheath expansion, and wave–particle interactions, and can be exploited for more accurate quantitative comparisons with experimental observations.

Design flow for efficient FPGA reconfiguration

In Run Time Reconfiguration (RTR) systems, the amount of reconfiguration is considerable when compared to the circuit changes implemented. This is because reconfiguration is not considered as part of the design flow. This paper presents a method for reconfigurable circuit design by modeling the underlying FPGA reconfigurable circuitry and taking it into consideration in the system design. This is demonstrated for an image processing example on the Xilinx Virtex FPGA.