Sonic Places: In Conversation with Peter Cusack

In this interview, Recomposing the City co-directors Sarah Lappin and Gascia Ouzounian talk with Peter Cusack about his recent work, reflecting in particular on relationships between sound, sound art, planning processes and urban communities. Cusack, a field recordist and sound artist, has been a leading figure in acoustic ecology and soundscape studies for more than two decades

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.

Concentration and purification of entanglement for qubit systems with ancillary cavity fields

We propose schemes for entanglement concentration and purification for qubit systems encoded in flying atomic pairs. We use cavity-quantum electrodynamics as an illustrative setting within which our proposals can be implemented. Maximally entangled pure states of qubits can be produced as a result of our protocols. In particular, the concentration protocol yields Bell states with the largest achievable theoretical probability while the purification scheme produces arbitrarily pure Bell states. The requirements for the implementation of these protocols are modest, within the state of the art, and we address all necessary steps in two specific setups based on experimentally mature microwave technology.

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.

Governance and charities: An exploration of key themes and the development of a research agenda

The concept of governance has been widely discussed in both the business and non-business sectors. The debate has also been entered into within the charity sector, which comprises over 169,000 organizations in the UK. The UK-based Charity Commission, which describes itself as existing to ‘promote sound governance and accountability’, has taken a lead in this debate by promoting greater regulation and producing numerous recommendations with regard to the proper governance of charitable organizations. However, the concept of what is meant by governance is unclear and a myriad of ideas are placed under the umbrella of ‘good governance’. This paper explores the major themes that form the basis of much of this discussion, examining both the theoretical underpinnings and empirical investigations relating to this area (looking from the perspective of the key stakeholders in the charity sector). Based on an analysis of the extant literature, this paper presents a broad definition of governance with respect to charities and outlines a future research agenda for those interested in adding to knowledge in this area.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Low-cost digital signature architecture suitable for radio frequency identification tags

Continuing achievements in hardware technology are bringing ubiquitous computing closer to reality. The notion of a connected, interactive and autonomous environment is common to all sensor networks, biosystems and radio frequency identification (RFID) devices, and the emergence of significant deployments and sophisticated applications can be expected. However, as more information is collected and transmitted, security issues will become vital for such a fully connected environment. In this study the authors consider adding security features to low-cost devices such as RFID tags. In particular, the authors consider the implementation of a digital signature architecture that can be used for device authentication, to prevent tag cloning, and for data authentication to prevent transmission forgery. The scheme is built around the signature variant of the cryptoGPS identification scheme and the SHA-1 hash function. When implemented on 130 nm CMOS the full design uses 7494 gates and consumes 4.72 mu W of power, making it smaller and more power efficient than previous low-cost digital signature designs. The study also presents a low-cost SHA-1 hardware architecture which is the smallest standardised hash function design to date.

Anthropology, Socialist Prediction and William Morris’s Commonweal

In the late nineteenth century, a number of writers turned to anthropology to predict a socialist future. They included prominent revolutionary socialists: Friedrich Engels, William Morris and members of the Socialist League. Contextualising the appropriation of the anthropologist Lewis Henry Morgan by such readers, this article also pays particular attention to socialist popularisations of anthropology, particularly those by Morris and his fellow writers in his penny weekly, the Commonweal. Focusing on Morris’s articles on ancient society helps to illuminate his own understanding of history, art and socialism. It also sheds new light on his predictive fiction News from Nowhere, which was originally read alongside Commonweal non-fiction. Both, I will argue, encouraged readers to see the future in the struggles of the ancient past.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.