FPGA Prototyping of Emerging Manycore Architectures for Parallel Programming Research using Formic Boards

Performance evaluation of parallel software and architectural exploration of innovative hardware support face a common challenge with emerging manycore platforms: they are limited by the slow running time and the low accuracy of software simulators. Manycore FPGA prototypes are difficult to build, but they offer great rewards. Software running on such prototypes runs orders of magnitude faster than current simulators. Moreover, researchers gain significant architectural insight during the modeling process. We use the Formic FPGA prototyping board [1], which specifically targets scalable and cost-efficient multi-board prototyping, to build and test a 64-board model of a 512-core, MicroBlaze-based, non-coherent hardware prototype with a full network-on-chip in a 3D-mesh topology. We expand the hardware architecture to include the ARM Versatile Express platforms and build a 520-core heterogeneous prototype of 8 Cortex-A9 cores and 512 MicroBlaze cores. We then develop an MPI library for the prototype and evaluate it extensively using several bare-metal and MPI benchmarks. We find that our processor prototype is highly scalable, models faithfully single-chip multicore architectures, and is a very efficient platform for parallel programming research, being 50,000 times faster than software simulation.

Rigorous Specification and Low-Latency Implementation of Technical Market Indicators

Technical market indicators are tools used by technical an- alysts to understand trends in trading markets. Technical (market) indicators are often calculated in real-time, as trading progresses. This paper presents a mathematically- founded framework for calculating technical indicators. Our framework consists of a domain specific language for the un- ambiguous specification of technical indicators, and a run- time system based on Click, for computing the indicators. We argue that our solution enhances the ease of program- ming due to aligning our domain-specific language to the mathematical description of technical indicators, and that it enables executing programs in kernel space for decreased latency, without exposing the system to users’ programming errors.

Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures

This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demon- strates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.

Derivation of scientific software from mathematical specifications

Often the modification and enhancement of large scientific software systems are severely hampered because many components of the system are written in an implementation dependent fashion, they are inadequately documented, and their functionalities are not precisely known. In this paper we consider how mathematics may be employed to alleviate some of these problems. In particular, we illustrate how the formal specification notation VDM-SL is being used to specify precisely abstract data types for use in the development of scientific software.

A SPECIFICATION OF A COMPLEX PROGRAMMING LANGUAGE STATEMENT

A formal specification of a complex programming language statement is presented. The subject matter was selected as being typical of the kind confronting a small software house. It is shown that formal specification notations may be applied, with benefit, to 'messy' problems. Emphasis is placed upon producing a specification which is readable by, and useful to a reader not familiar with formal notations.

Mathematical anxiety is linked to reduced cognitive reflection: A potential road from discomfort in the mathematics classroom to susceptibility to biases

Background
When asked to solve mathematical problems, some people experience anxiety and threat, which can lead to impaired mathematical performance (Curr Dir Psychol Sci 11:181–185, 2002). The present studies investigated the link between mathematical anxiety and performance on the cognitive reflection test (CRT; J Econ Perspect 19:25–42, 2005). The CRT is a measure of a person’s ability to resist intuitive response tendencies, and it correlates strongly with important real-life outcomes, such as time preferences, risk-taking, and rational thinking.

Methods
In Experiments 1 and 2 the relationships between maths anxiety, mathematical knowledge/mathematical achievement, test anxiety and cognitive reflection were analysed using mediation analyses. Experiment 3 included a manipulation of working memory load. The effects of anxiety and working memory load were analysed using ANOVAs.

Results
Our experiments with university students (Experiments 1 and 3) and secondary school students (Experiment 2) demonstrated that mathematical anxiety was a significant predictor of cognitive reflection, even after controlling for the effects of general mathematical knowledge (in Experiment 1), school mathematical achievement (in Experiment 2) and test anxiety (in Experiments 1–3). Furthermore, Experiment 3 showed that mathematical anxiety and burdening working memory resources with a secondary task had similar effects on cognitive reflection.

Conclusions
Given earlier findings that showed a close link between cognitive reflection, unbiased decisions and rationality, our results suggest that mathematical anxiety might be negatively related to individuals’ ability to make advantageous choices and good decisions.

Design patterns percolating to parallel programming framework implementation

Structured parallel programming is recognised as a viable and effective means of tackling parallel programming problems. Recently, a set of simple and powerful parallel building blocks RISC pb²l) has been proposed to support modelling and implementation of parallel frameworks. In this work we demonstrate how that same parallel building block set may be used to model both general purpose parallel programming abstractions, not usually listed in classical skeleton sets, and more specialized domain specific parallel patterns. We show how an implementation of RISC pb² l can be realised via the FastFlow framework and present experimental evidence of the feasibility and efficiency of the approach.