Distinct patterns of peripheral HIV-1-specific interferon- gamma responses in exposed HIV-1-seronegative individuals.

It is unclear how human immunodeficiency virus (HIV) type 1–specific immune responses in exposed seronegative (ESN) individuals differ from those in HIV-1–infected subjects. By use of overlapping peptides spanning Gag, Tat, Nef, Vif, Vpr, and Vpu, peripheral blood mononuclear cells from ESN individuals, their seropositive (SP) partners, and unexposed seronegative control subjects were screened for interferon-? production. Responses were more frequent (95.7% vs. 20%), of a higher magnitude (9-fold), and of wider breadth (median number of peptides recognized, 18 vs. 2.5) in SP than in ESN individuals. Peptides recognized by ESN individuals were less frequently recognized by their SP partners. SP subjects infrequently recognized peptides from Vif, and such responses were subdominant; among ESN individuals, this HIV-1 protein was most frequently recognized. Immunodominant peptides recognized by SP subjects tended to be from relatively conserved regions, whereas peptides recognized by ESN individuals were associated with slow disease progression.

Gold imidazolium-based ionic liquids, efficient catalysts for cycloisomerization of gamma-acetylenic carboxylic acids

Ionic liquid stabilized gold(III) chloride is shown to be a very active catalyst in the cyclization of sterically hindered and unhindered acetylenic carboxylic acid substrates even in the absence of a base.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.