Custom coprocessor based matrix algorithms for image and signal processing

Matrix algorithms are important in many types of applications including image and signal processing. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix algorithms such as matrix multiplication. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using a novel custom coprocessor system for MATrix algorithms based on Reconfigurable Computing (RCMAT). The proposed RCMAT architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.

Power Efficient DSP Datapath Configuration Methodology for FPGA

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Ultra-lightweight true random number generators

A series of ultra-lightweight digital true random number generators (TRNGs) are presented. These TRNGs are based on the observation that, when a circuit switches from a metastable state to a bi-stable state, the resulting state may be random. Four such circuits with low hardware cost are presented: one uses an XOR gate; one uses a lookup table; one uses a multiplexer and an inverter; and one uses four transistors. The three TRNGs based on the first three circuits are implemented on a field programmable gate array and successfully pass the DIEHARD RNG tests and the National Institute of Standard and Technology (NIST) RNG tests. To the best of the authors' knowledge, the proposed TRNG designs are the most lightweight among existing TRNGs.

Deep molluscan phylogeny: synthesis of palaeontological and neontological data

The position of the earliest-derived living molluscs, the Polyplacophora ( chitons) and shell-less vermiform Aplacophora, remains highly contentious despite many morphological, developmental and molecular studies of extant organisms. These two groups are thought to represent either a basal molluscan grade or a clade (Aculifera) sister to the 'higher' molluscs (Conchifera). These incompatible hypotheses result in very different predictions about the earliest molluscs. A new cladistic analysis incorporating both Palaeozoic and extant molluscs is presented here. Our results support the monophyly of Aculifera and suggest that extant aplacophorans and polyplacophorans both derive from a disparate group of multivalved molluscs in two major clades. Reanalysis of the critical Ordovician taxon 'Helminthochiton' thraivensis shows that this animal lacks a true foot despite bearing polyplacophoran-like valves. Its position within our phylogenetic reconstruction indicates that many fossil 'polyplacophorans' in the order Palaeoloricata are likely to represent footless stem-group aplacophorans. 'H.' thraivensis and similar forms such as Acaenoplax may be morphological stepping stones between chitons and the shell-less aplacophorans. Our results imply that crown-group molluscan synapomorphies include serial repetition, the presence of a foot, a mineralized scleritome and a creeping rather than worm-like mode of life.

Primitive living chitons: Morphological cladistic analysis as a model for character evaluation

Chitons are often referred to as “living fossils” in part because they are proposed as one of the earliest-diverging groups of living molluscs, but also because the gross morphology of the polyplacophoran shell has been conserved for hundreds of millions of years. As such, the analysis of evolution and radiation within polyplacophorans is of considerable interest not only for resolving the shape of pan-molluscan phylogeny but also as model organisms for the study of character evolution. This study presents a new, rigorous cladistic analysis of the morphological characters used in taxonomic descriptions for chitons in the living suborder Lepidopleurina Thiele, 1910 (the earliest-derived living group of chitons). Shell-based characters alone entirely fail to recover any recognized subdivisions within the group, which may raise serious questions about the application of fossil data (from isolated shell valves). New analysis including characters from girdle armature and gill arrangements recovers some genera within the group but also points to the lack of monophyly within the main genus Leptochiton Gray, 1847. Additional characters from molecular data and soft anatomy, used in combination, are clearly needed to resolve questions of chiton relationships. However, the data sets currently available already provide interesting insights into the analytical power of traditional morphology as well as some knowledge about the early evolution and radiation of this group.

Evaluation of Random Delay Insertion against DPA on FPGAs

Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks. Numerous countermeasure techniques, such as Random Delay Insertion (RDI), have been proposed to reduce the risk of DPA attacks against cryptographic devices. The RDI technique was first proposed for microprocessors but it was shown to be unsuccessful when implemented on smartcards as it was vulnerable to a variant of the DPA attack known as the Sliding-Window DPA attack.Previous research by the authors investigated the use of the RDI countermeasure for Field Programmable Gate Array (FPGA) based cryptographic devices. A split-RDI technique wasproposed to improve the security of the RDI countermeasure. A set of critical parameters wasalso proposed that could be utilized in the design stage to optimize a security algorithm designwith RDI in terms of area, speed and power. The authors also showed that RDI is an efficientcountermeasure technique on FPGA in comparison to other countermeasures.In this article, a new RDI logic design is proposed that can be used to cost-efficiently implementRDI on FPGA devices. Sliding-Window DPA and realignment attacks, which were shown to beeffective against RDI implemented on smartcard devices, are performed on the improved RDIFPGA implementation. We demonstrate that these attacks are unsuccessful and we also proposea realignment technique that can be used to demonstrate the weakness of RDI implementations.

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with runtime reconfigurability. We present a softcore-processor based solution to this issue, and show for the first time, that such programmable architectures can enable real-time data operation for cutting-edge standards
such as 802.11n; furthermore, by exploiting deep processing pipelines and interleaved task execution, the cost and performance of these architectures is shown to be on a par with traditional dedicated circuit based solutions. We believe this to be the first such programmable architecture to achieve this, and the combination of implementation efficiency and programmability makes this implementation style the most promising approach for hosting such dynamic architectures.