Improved power-saving medium access protocol for IEEE 802.11e QoS-enabled wireless networks

The performance of a new pointer-based medium-access control protocol that was designed to significantly improve the energy efficiency of user terminals in quality-of-service-enabled wireless local area networks was analysed. The new protocol, pointer-controlled slot allocation and resynchronisation protocol (PCSARe), is based on the hybrid coordination function-controlled channel access mode of the IEEE 802.11e standard. PCSARe reduces energy consumption by removing the need for power-saving stations to remain awake for channel listening. Discrete event network simulations were performed to compare the performance of PCSARe with the non-automatic power save delivery (APSD) and scheduled-APSD power-saving modes of IEEE 802.11e. The simulation results show a demonstrable improvement in energy efficiency without significant reduction in performance when using PCSARe. For a wireless network consisting of an access point and eight stations in power-saving mode, the energy saving was up to 39% when using PCSARe instead of IEEE 802.11e non-APSD. The results also show that PCSARe offers significantly reduced uplink access delay over IEEE 802.11e non-APSD, while modestly improving the uplink throughput. Furthermore, although both had the same energy consumption, PCSARe gave a 25% reduction in downlink access delay compared with IEEE 802.11e S-APSD.

Modeling energy consumption in error-prone IEEE 802.11-based wireless ad-hoc networks

In the IEEE 802.11 MAC layer protocol, there are different trade-off points between the number of nodes competing for the medium and the network capacity provided to them. There is also a trade-off between the wireless channel condition during the transmission period and the energy consumption of the nodes. Current approaches at modeling energy consumption in 802.11 based networks do not consider the influence of the channel condition on all types of frames (control and data) in the WLAN. Nor do they consider the effect on the different MAC and PHY schemes that can occur in 802.11 networks. In this paper, we investigate energy consumption corresponding to the number of competing nodes in IEEE 802.11's MAC and PHY layers in error-prone wireless channel conditions, and present a new energy consumption model. Analysis of the power consumed by each type of MAC and PHY over different bit error rates shows that the parameters in these layers play a critical role in determining the overall energy consumption of the ad-hoc network. The goal of this research is not only to compare the energy consumption using exact formulae in saturated IEEE 802.11-based DCF networks under varying numbers of competing nodes, but also, as the results show, to demonstrate that channel errors have a significant impact on the energy consumption.

Randomized caches for power-efficiency

Embedded processors are used in numerous devices executing dedicated applications. This setting makes it worthwhile to optimize the processor to the application it executes, in order to increase its power-efficiency. This paper proposes to enhance direct mapped data caches with automatically tuned randomized set index functions to achieve that goal. We show how randomization functions can be automatically generated and compare them to traditional set-associative caches in terms of performance and energy consumption. A 16 kB randomized direct mapped cache consumes 22% less energy than a 2-way set-associative cache, while it is less than 3% slower. When the randomization function is made configurable (i.e., it can be adapted to the program), the additional reduction of conflicts outweighs the added complexity of the hardware, provided there is a sufficient amount of conflict misses.

Researcher identity: exploring the transformatory power of the research experience.

In consumer research, we frequently focus on the phenomenon of transformation, whether the transformatory effects of a particular consumption community or the great body of work being carried out under the banner of transformative consumer research. However, there is a particular transformation which occurs in the field of interpretivist consumer research that, we would argue, is overlooked—that of researcher transformation. We present as data our reflexive considerations on the ways in which our own research with vulnerable consumers has affected and changed us. We consider short-term transformations in the field, reflecting on the various ways that researcher identity is carefully managed and negotiated to fit with the social–cultural setting. We also consider longer term transformations and discuss the enduring impact of the research process—the people we have met, the homes we have visited, and the stories we have heard. By reflecting on the shaping of identities ‘in the field’, we aim to deepen our appreciation of the interpretive consumer research process and contribute to theoretical understanding of transformative identity research. Copyright © 2012 John Wiley & Sons, Ltd.

Power take-off and damping of an oscillating wave surge converter

The European Union has set a target of 20% for the share of renewable energy sources in gross final energy consumption in 2020. These renewable energy targets are priority objectives for the Europe 2020 strategy for inclusive growth. In line with the European Union renewable energy policies, the Northern Ireland Executive has a target to deliver 40% renewable electricity by 2020. Currently, Northern Ireland imports 98% of the energy it uses in the form of fossil fuels. Locally produced energy and electricity is needed to ensure sustainable development. The aim of this research is to develop part of a strategy for the mechanical power take-off system for a flap type wave energy converter. Aquamarine Power Ltd’s Oyster flap was the device used for simulation and testing purposes. In this paper the state-of-the-art of wave energy converters is reviewed and a 40th scale test model was developed and built.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Power and Energy Implications of the Number of Threads Used on the Intel Xeon Phi

Energy consumption has become an important area of research of late. With the advent of new manycore processors, situations have arisen where not all the processors need to be active to reach an optimal relation between performance and energy usage. In this paper a study of the power and energy usage of a series of benchmarks, the PARSEC and the SPLASH- 2X Benchmark Suites, on the Intel Xeon Phi for different threads configurations, is presented. To carry out this study, a tool was designed to monitor and record the power usage in real time during execution time and afterwards to compare the r

Optimal Scheduling Methods to Integrate Plug-In Electric Vehicles with the Power System: A Review

The introduction of the Tesla in 2008 has demonstrated to the public of the potential of electric vehicles in terms of reducing fuel consumption and green-house gas from the transport sector. It has brought electric vehicles back into the spotlight worldwide at a moment when fossil fuel prices were reaching unexpected high due to increased demand and strong economic growth. The energy storage capabilities from of fleets of electric vehicles as well as the potentially random discharging and charging offers challenges to the grid in terms of operation and control. Optimal scheduling strategies are key to integrating large numbers of electric vehicles and the smart grid. In this paper, state-of-the-art optimization methods are reviewed on scheduling strategies for the grid integration with electric vehicles. The paper starts with a concise introduction to analytical charging strategies, followed by a review of a number of classical numerical optimization methods, including linear programming, non-linear programming, dynamic programming as well as some other means such as queuing theory. Meta-heuristic techniques are then discussed to deal with the complex, high-dimensional and multi-objective scheduling problem associated with stochastic charging and discharging of electric vehicles. Finally, future research directions are suggested.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Control energy consumption and system performance in vector control of voltage source converters

Power electronics plays an important role in the control and conversion of modern electric power systems. In particular, to integrate various renewable energies using DC transmissions and to provide more flexible power control in AC systems, significant efforts have been made in the modulation and control of power electronics devices. Pulse width modulation (PWM) is a well developed technology in the conversion between AC and DC power sources, especially for the purpose of harmonics reduction and energy optimization. As a fundamental decoupled control method, vector control with PI controllers has been widely used in power systems. However, significant power loss occurs during the operation of these devices, and the loss is often dissipated in the form of heat, leading to significant maintenance effort. Though much work has been done to improve the power electronics design, little has focused so far on the investigation of the controller design to reduce the controller energy consumption (leading to power loss in power electronics) while maintaining acceptable system performance. This paper aims to bridge the gap and investigates their correlations. It is shown a more thoughtful controller design can achieve better balance between energy consumption in power electronics control and system performance, which potentially leads to significant energy saving for integration of renewable power sources.

Inexact-aware architecture design for ultra-low power bio-signal analysis

This study introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimise energy consumption. In this scenario, the reliability of static RAM (SRAM) memories cannot be guaranteed when using conventional 6-transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near-threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, the authors propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e. their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. The authors illustrate their scheme on an industrial benchmark application performing the power spectrum analysis of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.