Position control of shape memory alloy actuators using self tuning fuzzy PID controller

Shape Memory Alloy (SMA) actuators, which have the ability to return to a predetermined shape when heated, have many potential applications such as aeronautics, surgical tools, robotics and so on. Although the conventional PID controller can be used with slow response systems, there has been limited success in precise motion control of SMA actuators, since the systems are disturbed by unknown factors beside their inherent nonlinear hysteresis and changes in the surrounding environment of the systems. This paper presents a new development of a SMA position control system by using a self-tuning fuzzy PID controller. This control algorithm is used by tuning the parameters of the PID controller thereby integrating fuzzy inference and producing a fuzzy adaptive PID controller, which can then be used to improve the control performance of nonlinear systems. The experimental results of position control of SMA actuators using conventional and self-tuning fuzzy PID controllers are both included in this paper.

Internal model control for shape memory alloy actuators using fuzzy based Preisach model

This paper investigates a possible application of Preisach model to control shape memory alloy (SMA) actuators using an internal model control strategy. The developed strategy consists in including the Preisach hysteresis model of SMA actuator and the inverse Preisach model within the control structure. In this work, an extrema input hystory and a fuzzy inference is utilized to replace the classical Preisach model. This allows to reduce a large amount of experimental parameters and computation time of the classical Preisach model. To demonstrate the effectiveness of the proposed controller in improving control performance and hysteresis compensation of SMA actuators, experimental results from real time control are presented.

Trajectory Control of Electro Hydraulic Excavator using Fuzzy Self Tuning Algorithm with Neural Network

This paper presents the trajectory control of a 2DOF mini electro-hydraulic excavator by using fuzzy self tuning with neural network algorithm. First, the mathematical model is derived for the 2DOF mini electro-hydraulic excavator. The fuzzy PID and fuzzy self tuning with neural network are designed for circle trajectory following. Its two links are driven by an electric motor controlled pump system. The experimental results demonstrated that the proposed controllers have better control performance than the conventional controller.

Modelling and Control of Shape Memory Alloy Actuators by using Preisach Model, Genetic Algorithm and Fuzzy Logic

Shapememoryalloy (SMA) actuators, which have the ability to return to a predetermined shape when heated, have many potential applications in aeronautics, surgical tools, robotics and so on. Nonlinearity hysteresis effects existing in SMA actuators present a problem in the motion control of these smart actuators. This paper investigates the control problem of SMA actuators in both simulation and experiment. In the simulation, the numerical Preisachmodel with geometrical interpretation is used for hysteresis modeling of SMA actuators. This model is then incorporated in a closed loop PID control strategy. The optimal values of PID parameters are determined by using geneticalgorithm to minimize the mean squared error between desired output displacement and simulated output. However, the control performance is not good compared with the simulation results when these parameters are applied to the real SMA control since the system is disturbed by unknown factors and changes in the surrounding environment of the system. A further automated readjustment of the PID parameters using fuzzylogic is proposed for compensating the limitation. To demonstrate the effectiveness of the proposed controller, real time control experiment results are presented.

VLSI processor for high-performance arithmetic computations

A high performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform one or more of these operations. The throughput rate for each operation is the same and is wordlength independent. This is achieved using redundant arithmetic. With current CMOS technology, throughput rates in excess of 80 million operations per second are expected.

Distinguished algebraic semantics for t-norm based fuzzy logics:Methods and algebraic equivalencies

This paper is a contribution to Mathematical fuzzy logic, in particular to the algebraic study of t-norm based fuzzy logics. In the general framework of propositional core and ?-core fuzzy logics we consider three properties of completeness with respect to any semantics of linearly ordered algebras. Useful algebraic characterizations of these completeness properties are obtained and their relations are studied. Moreover, we concentrate on five kinds of distinguished semantics for these logics-namely the class of algebras defined over the real unit interval, the rational unit interval, the hyperreals (all ultrapowers of the real unit interval), the strict hyperreals (only ultrapowers giving a proper extension of the real unit interval) and finite chains, respectively-and we survey the known completeness methods and results for prominent logics. We also obtain new interesting relations between the real, rational and (strict) hyperreal semantics, and good characterizations for the completeness with respect to the semantics of finite chains. Finally, all completeness properties and distinguished semantics are also considered for the first-order versions of the logics where a number of new results are proved. © 2009 Elsevier B.V. All rights reserved.

Cognitive and task-related EEG correlates of arithmetic performance in adolescents

Cognitive and neurophysiological correlates of arithmetic calculation, concepts, and applications were examined in 41 adolescents, ages 12-15 years. Psychological and task-related EEG measures which correctly distinguished children who scored low vs. high (using a median split) in each arithmetic subarea were interpreted as indicative of processes involved. Calculation was related to visual-motor sequencing, spatial visualization, theta activity measured during visual-perceptual and verbal tasks at right- and left-hemisphere locations, and right-hemisphere alpha activity measured during a verbal task. Performance on arithmetic word problems was related to spatial visualization and perception, vocabulary, and right-hemisphere alpha activity measured during a verbal task. Results suggest a complex interplay of spatial and sequential operations in arithmetic performance, consistent with processing model concepts of lateralized brain function.

Adaptive Measurement-Based Policy-Driven QoS Management with Fuzzy-Rule-based Resource Allocation

Fixed and wireless networks are increasingly converging towards common connectivity with IP-based core networks. Providing effective end-to-end resource and QoS management in such complex heterogeneous converged network scenarios requires unified, adaptive and scalable solutions to integrate and co-ordinate diverse QoS mechanisms of different access technologies with IP-based QoS. Policy-Based Network Management (PBNM) is one approach that could be employed to address this challenge. Hence, a policy-based framework for end-to-end QoS management in converged networks, CNQF (Converged Networks QoS Management Framework) has been proposed within our project. In this paper, the CNQF architecture, a Java implementation of its prototype and experimental validation of key elements are discussed. We then present a fuzzy-based CNQF resource management approach and study the performance of our implementation with real traffic flows on an experimental testbed. The results demonstrate the efficacy of our resource-adaptive approach for practical PBNM systems

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Parental leave regulations and the persistence of the male breadwinner model: Using fuzzy-set ideal type analysis to assess gender equality in an enlarged Europe

his paper uses fuzzy-set ideal type analysis to assess the conformity of European leave regulations to four theoretical ideal typical divisions of labour: male breadwinner, caregiver parity, universal breadwinner and universal caregiver. In contrast to the majority of previous studies, the focus of this analysis is on the extent to which leave regulations promote gender equality in the family and the transformation of traditional gender roles. The results of this analysis demonstrate that European countries cluster into five models that only partly coincide with countries’ geographical proximity. Second, none of the countries considered constitutes a universal caregiver model, while the male breadwinner ideal continues to provide the normative reference point for parental leave regulations in a large number of European states. Finally, we witness a growing emphasis at the national and EU levels concerning the universal breadwinner ideal, which leaves gender inequality in unpaid work unproblematized.