Global Quantum Correlation in the Ising model

We study quantum correlations in an isotropic Ising ring under the effects of a transverse magnetic field. After characterizing the behavior of two-spin quantum correlations, we extend our analysis to global properties of the ring, using a figure of merit for quantum correlations that shows enough sensitivity to reveal the drastic changes in the properties of the system at criticality. This opens up the possibility to relate statistical properties of quantum many-body systems to suitably tailored measures of quantum correlations that capture features going far beyond standard quantum entanglement.

Software-defined sphere decoding for FPGA-based MIMO detection

Sphere Decoding (SD) is a highly effective detection technique for Multiple-Input Multiple-Output (MIMO) wireless communications receivers, offering quasi-optimal accuracy with relatively low computational complexity as compared to the ideal ML detector. Despite this, the computational demands of even low-complexity SD variants, such as Fixed Complexity SD (FSD), remains such that implementation on modern software-defined network equipment is a highly challenging process, and indeed real-time solutions for MIMO systems such as 4 4 16-QAM 802.11n are unreported. This paper overcomes this barrier. By exploiting large-scale networks of fine-grained softwareprogrammable processors on Field Programmable Gate Array (FPGA), a series of unique SD implementations are presented, culminating in the only single-chip, real-time quasi-optimal SD for 44 16-QAM 802.11n MIMO. Furthermore, it demonstrates that the high performance software-defined architectures which enable these implementations exhibit cost comparable to dedicated circuit architectures.

Stress correlation between instrumentation and simulation analysis of the die for high pressure die casting

A strain gauge instrumentation trial on a high pressure die casting ‘HPDC’ die was compared to a corresponding simulation model using Magmasoft® casting simulation software at two strain gauge rosette locations. The strains were measured during the casting cycle, from which the von Mises stress was determined and then compared to the simulation model. The von Mises stress from the simulation model correlated well with the findings from the instrumentation trial, showing a difference of 5.5%, ~ 10 MPa for one strain gauge rosette located in an area of low stress gradient. The second rosette was in a region of steep stress gradient, which resulted in a difference of up to 40%, ~40 MPa between the simulation and instrumentation results. Factors such as additional loading from die closure force or metal injection pressure which are not modelled by Magmasoft® were seen to have very little influence on the stress in the die, less than 7%.

FIBRE-OPTIC MULTICHANNEL CORRELATION/CONVOLUTION.

A fiber-optic multichannel correlator/convolver based on a two-dimensional systolic array architecture is described. Experimental verification of processor performance is presented.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.