An Improvement of IP Address Lookup based on Rule Filter Analysis

Multi-bit trie is a popular approach performing the longest prefix matching for packet classification. However, it requires a long lookup time and inefficiently consumes memory space. This paper presents an in-depth study of different variations of multi-bit trie for IP address lookup. Our main aim is to study a method of data structure which reduces memory space. The proposed approach has been implemented using the label method in two approaches. Both methods present better results regarding lookup speed, update time and memory bit consumptions.

The influence of high air entry filter on the testing of unsaturated soils using the axis translation technique

Suction is an important stress variable that is required for reliable predictions of the likely performance of unsaturated soils. The axis translation technique is the best established method of measuring or controlling suction; however, the success of this application is heavily dependent on the rating of the high air entry filter (HAF) and how it is incorporated into the testing system. This paper reports some basic experiments in which samples of unsaturated kaolin were brought to saturation in stages using 5 bar and 15 bar HAFs. The results have shown that the water equilibrium in unsaturated soils is greatly affected by the rating of filters. The findings also suggest that the flow through unsaturated soils is not necessarily governed by the one-dimensional consolidation theory that was developed for saturated soils, and this may be attributed to the bimodal pore size distribution of unsaturated soils.

A high performance IIR digital filter chip

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.

Dynamic State Estimation of Power Systems with Quantization Eects: A Recursive Filter Approach

In this paper, a recursive filter algorithm is developed to deal with the state estimation problem for power systems with quantized nonlinear measurements. The measurements from both the remote terminal units and the phasor measurement unit are subject to quantizations described by a logarithmic quantizer. Attention is focused on the design of a recursive filter such that, in the simultaneous presence of nonlinear measurements and quantization effects, an upper bound for the estimation error covariance is guaranteed and subsequently minimized. Instead of using the traditional approximation methods in nonlinear estimation that simply ignore the linearization errors, we treat both the linearization and quantization errors as norm-bounded uncertainties in the algorithm development so as to improve the performance of the estimator. For the power system with such kind of introduced uncertainties, a filter is designed in the framework of robust recursive estimation, and the developed filter algorithm is tested on the IEEE benchmark power system to demonstrate its effectiveness.

Series-L/parallel-tuned Class-E power amplifier analysis

An analysis of the operation of a new series-L/parallel-tuned Class-E amplifier and its equivalence to the classic shunt-C/series-tuned Class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given, including the switch current and voltage in steady state, the circuit component values, the peak values of switch current and voltage and the power-output capability. Theoretical analysis is confirmed by numerical simulation for a 500 mW (27 dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned Class-E power amplifier, operating at 2.5 GHz. Excellent agreement between theory and simulation results is achieved.