The impact of global routing on the performance of NoCs in FPGAs

With the over-provisioned routing resource on FPGA, the topology choice for NoC implementation on FPGA is more flexible than on ASIC. However, it is well understood that the global wire routing impacts the performance of NoC on FPGA because the topology is routed by using fixed routing fabric. An important question that arises is: will the benefit of diameter reduction by using a highly connective topology outweigh the impact of global routing? To answer this question, we investigate FPGA based packet switched NoC implementations with different sizes and topologies, and quantitatively measure the impact of global routing to each of these networks. The result shows that with sufficient routing resources on modern FPGA, the global routing is not on the critical path of the system, and thus is not a dominating factor for the performance of practical multi-hop NoC system. © 2011 IEEE.

Multi-standard sub-pixel interpolation architecture for video motion estimation

A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video Motion Estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard. ©2008 IEEE.

Pilot Tone Actuated Antenna Array Pattern Reconfiguration

A new strategy for remote reconfiguration of an antenna array far field radiation pattern is described. The scheme uses a pilot tone co-transmitted with a carrier signal from a location distant from that of a receive antenna array whose far field pattern is to be reconfigured. By mixing the co-transmitted signals locally at each antenna element in the array an IF signal is formed which defines an equivalent array spacing that can be made variable by tuning the frequency of the pilot tone with respect to the RF carrier. This makes the antenna array factor hence far field spatial characteristic reconfigurable on receive. For a 10 x 1 microstrip patch element array we show that the receive pattern can be made to vary from 35 to 10 degrees half power beam width as the difference frequency between the pilot and the carrier at 2.45 GHz varies between 10 MHz and 500 MHz carrier.

NanoStreams: Advancing the Hardware and Software Stack for Real-Time Analytics on Fast Data Streams

NanoStreams is a consortium project funded by the European Commission under its FP7 programme and is a major effort to address the challenges of processing vast amounts of data in real-time, with a markedly lower carbon footprint than the state of the art. The project addresses both the energy challenge and the high-performance required by emerging applications in real-time streaming data analytics. NanoStreams achieves this goal by designing and building disruptive micro-server solutions incorporating real-silicon prototype micro-servers based on System-on-Chip and reconfigurable hardware technologies.

Type Synthesis of 3-DOF Multi-Mode Translational/Spherical Parallel Mechanisms with Lockable Joints

A 3-DOF (degrees-of-freedom) multi-mode translational/spherical PM (parallel mechanism) with lockable joints is a novel reconfigurable PM. It has both 3-DOF spatial translational operation mode and 3-DOF spherical operation mode. This paper presents an approach to the type synthesis of translational/spherical PMs with lockable joints. Using the proposed approach, several 3-DOF translational/spherical PMs are obtained. It is found that these translational/spherical PMs do not encounter constraint singular configurations and self-motion of sub-chain of a leg during reconfiguration. The approach can also be used for synthesizing other classes of multi-mode PMs with lockable joints, multi-mode PMs with variable kinematic joints, partially decoupled PMs, and reconfigurable PMs with a reconfigurable platform.

Active singly and dual polarised interwoven spiral frequency selective surfaces

Reconfigurable bi-state interwoven spiral FSSs are explored in this work. Their switching capability is realized by pin diodes that enable the change of the electromagnetic response between transparent and reflecting modes at the specified frequencies in both singly and dual polarised unit cell configurations. The proposed topologies are single layer FSS with their elements acting also as dc current carrying conductors supplying the bias signal for switching pin diodes between the on and off states, thus avoiding the need of external bias lines that can cause parasitic resonances and affect the response at oblique incidence. The presented simulation results show that such active FSSs have potentially good isolation between the transmission and reflection states, while retaining the substantially subwavelength response of the unit cell with large fractional bandwidths (FBWs) inherent to the original passive FSSs.

Conceptual Design and Workspace Analysis of an Exechon-inspired Parallel Kinematic Machine

Inspired by the commercial application of the Exechon machine, this paper proposed a novel parallel kinematic machine (PKM) named Exe-Variant. By exchanging the sequence of kinematic pairs in each limb of the Exechon machine, the Exe-Variant PKM claims an arrangement of 2UPR/1SPR topology and consists of two identical UPR limbs and one SPR limb. The inverse kinematics of the 2UPR/1SPR parallel mechanism was firstly analyzed based on which a conceptual design of the Exe-Variant was carried out. Then an algorithm of reachable workspace searching for the Exe-Variant and the Exchon was proposed. Finally, the workspaces of two example systems of the Exechon and the Exe-Variant with approximate dimensions were numerically simulated and compared. The comparison shows that the Exe-Variant possesses a competitive workspace with the Exechon machine, indicating it can be used as a promising reconfigurable module in a hybrid 5-DOF machine tool system.

Design and Demonstration of an Electronically Scanned Reflectarray Antenna at 100 GHz using Multiresonant Cells Based on Liquid Crystals

The design, fabrication, and measured results are presented for a reconfigurable reflectarray antenna based on liquid crystals (LCs)which operates above 100 GHz. The antenna has been designed to provide beam scanning capabilities over a wide angular range, a large bandwidth,and reduced side-lobe level (SLL). Measured radiation patterns are in good agreement with simulations, and show that the antenna generates an electronically steerable beam in one plane over an angular range of 55◦ in the frequency band from 96 to 104 GHz. The SLL is lower than −13 dB for all the scan angles and −18 dB is obtained over 16% of the scan range. The measured performance is significantly better than previously published results for this class of electronically tunable antenna, and moreover, veri-fies the accuracy of the proposed procedure for LC modeling and antenna design.

FPGA Soft-core Processors, Compiler and Hardware Optimizations validated using HOG

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.

FPGA based Streaming Image Processing Processor (SIPPro) architecture to accelerate data intensive applications

Current data-intensive image processing applications push traditional embedded architectures to their limits. FPGA based hardware acceleration is a potential solution but the programmability gap and time consuming HDL design flow is significant. The proposed research approach to develop “FPGA based programmable hardware acceleration platform” that uses, large number of Streaming Image processing Processors (SIPPro) potentially addresses these issues. SIPPro is pipelined in-order soft-core processor architecture with specific optimisations for image processing applications. Each SIPPro core uses 1 DSP48, 2 Block RAMs and 370 slice-registers, making the processor as compact as possible whilst maintaining flexibility and programmability. It is area efficient, scalable and high performance softcore architecture capable of delivering 530 MIPS per core using Xilinx Zynq SoC (ZC7Z020-3). To evaluate the feasibility of the proposed architecture, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the color and morphology operations accelerated using multiple SIPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 and 33 times for color filtering and morphology operations respectively, with a significant reduced design effort and time.

The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.

Emerging web applications like cloud computing, Big Data and social networks have created the need for powerful centres hosting hundreds of thousands of servers. Currently, the data centres are based on general purpose processors that provide high flexibility buts lack the energy efficiency of customized accelerators. VINEYARD aims to develop an integrated platform for energy-efficient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators. It will, also, build a high-level programming framework for allowing end-users to seamlessly utilize these accelerators in heterogeneous computing systems by employing typical data-centre programming frameworks (e.g. MapReduce, Storm, Spark, etc.). This programming framework will, further, allow the hardware accelerators to be swapped in and out of the heterogeneous infrastructure so as to offer high flexibility and energy efficiency. VINEYARD will foster the expansion of the soft-IP core industry, currently limited in the embedded systems, to the data-centre market. VINEYARD plans to demonstrate the advantages of its approach in three real use-cases (a) a bio-informatics application for high-accuracy brain modeling, (b) two critical financial applications, and (c) a big-data analysis application.

Optimal day-ahead scheduling of integrated urban energy systems

An optimal day-ahead scheduling method (ODSM) for the integrated urban energy system (IUES) is introduced, which considers the reconfigurable capability of an electric distribution network. The hourly topology of a distribution network, a natural gas network, the energy centers including the combined heat and power (CHP) units, different energy conversion devices and demand responsive loads (DRLs), are optimized to minimize the day-ahead operation cost of the IUES. The hourly reconfigurable capability of the electric distribution network utilizing remotely controlled switches (RCSs) is explored and discussed. The operational constraints from the unbalanced three-phase electric distribution network, the natural gas network, and the energy centers are considered. The interactions between the electric distribution network and the natural gas network take place through conversion of energy among different energy vectors in the energy centers. An energy conversion analysis model for the energy center was developed based on the energy hub model. A hybrid optimization method based on genetic algorithm (GA) and a nonlinear interior point method (IPM) is utilized to solve the ODSM model. Numerical studies demonstrate that the proposed ODSM is able to provide the IUES with an effective and economical day-ahead scheduling scheme and reduce the operational cost of the IUES.