ALEA: Fine-Grain Energy Profiling with Basic Block Sampling

Energy efficiency is an essential requirement for all contemporary computing systems. We thus need tools to measure the energy consumption of computing systems and to understand how workloads affect it. Significant recent research effort has targeted direct power measurements on production computing systems using on-board sensors or external instruments. These direct methods have in turn guided studies of software techniques to reduce energy consumption via workload allocation and scaling. Unfortunately, direct energy measurements are hampered by the low power sampling frequency of power sensors. The coarse granularity of power sensing limits our understanding of how power is allocated in systems and our ability to optimize energy efficiency via workload allocation.
We present ALEA, a tool to measure power and energy consumption at the granularity of basic blocks, using a probabilistic approach. ALEA provides fine-grained energy profiling via sta- tistical sampling, which overcomes the limitations of power sens- ing instruments. Compared to state-of-the-art energy measurement tools, ALEA provides finer granularity without sacrificing accuracy. ALEA achieves low overhead energy measurements with mean error rates between 1.4% and 3.5% in 14 sequential and paral- lel benchmarks tested on both Intel and ARM platforms. The sampling method caps execution time overhead at approximately 1%. ALEA is thus suitable for online energy monitoring and optimization. Finally, ALEA is a user-space tool with a portable, machine-independent sampling method. We demonstrate two use cases of ALEA, where we reduce the energy consumption of a k-means computational kernel by 37% and an ocean modelling code by 33%, compared to high-performance execution baselines, by varying the power optimization strategy between basic blocks.

Suitability, efficiency and microbiological safety of novel physical technologies for the processing of ready-to-eat meals, meats and pumpable products

Consumer studies and market reports show an increase in consumption of ready-to-eat (RTE) foods. Although conventional processing technologies can in most cases produce safe products, they can also lead to the degradation of nutritional compounds and negatively affect quality characteristics. Consumers strongly prefer food that is minimally processed with the maximum amount of health-promoting substances. Novel processing technologies as pre- or post-treatment decontamination methods or as substitutes of conventional technologies have the potential to produce foods that are safe, rich in nutrient content and with superior organoleptic properties. Combining novel with conventional processes can eliminate potential drawbacks of novel technologies. This review examines available scientific information and critically evaluates the suitability and efficiency of various novel thermal and nonthermal technologies in terms of microbial safety, quality as well as nutrient content on the production of RTE meals, meats and pumpable products.

Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.

Streaming Elements for FPGA Signal and Image Processing Accelerators

Field programmable gate array devices boast abundant resources with which custom accelerator components for signal, image and data processing may be realised; however, realising high performance, low cost accelerators currently demands manual register transfer level design. Software-programmable ’soft’ processors have been proposed as a way to reduce this design burden but they are unable to support performance and cost comparable to custom circuits. This paper proposes a new soft processing approach for FPGA which promises to overcome this barrier. A high performance, fine-grained streaming processor, known as a Streaming Accelerator Element, is proposed which realises accelerators as large scale custom multicore networks. By adopting a streaming execution approach with advanced program control and memory addressing capabilities, typical program inefficiencies can be almost completely eliminated to enable performance and cost which are unprecedented amongst software-programmable solutions. When used to realise accelerators for fast fourier transform, motion estimation, matrix multiplication and sobel edge detection it is shown how the proposed architecture enables real-time performance and with performance and cost comparable with hand-crafted custom circuit accelerators and up to two orders of magnitude beyond existing soft processors.

Cross-layer Framework for Fine-grained Channel Access in Next Generation High-density WiFi Networks

Densely deployed WiFi networks will play a crucial role in providing the capacity for next generation mobile internet. However, due to increasing interference, overlapped channels in WiFi networks and throughput efficiency degradation, densely deployed WiFi networks is not a guarantee to obtain higher throughput. An emergent challenge is how to efficiently utilize scarce spectrum resources, by matching physical layer resources to traffic demand. In this aspect, access control allocation strategies play a pivotal role but remain too coarse-grained. As a solution, this research proposes a flexible framework for fine-grained channel width adaptation and multi-channel access in WiFi networks. This approach, named SFCA (Sub-carrier Fine-grained Channel Access), adopts DOFDM (Discontinuous Orthogonal Frequency Division Multiplexing) at the PHY layer. It allocates the frequency resource with a sub-carrier granularity, which facilitates the channel width adaptation for multi-channel access and thus brings more flexibility and higher frequency efficiency. The MAC layer uses a frequency-time domain backoff scheme, which combines the popular time-domain BEB scheme with a frequency-domain backoff to decrease access collision, resulting in higher access probability for the contending nodes. SFCA is compared with FICA (an established access scheme) showing significant outperformance. Finally we present results for next generation 802.11ac WiFi networks.

FPGA based Streaming Image Processing Processor (SIPPro) architecture to accelerate data intensive applications

Current data-intensive image processing applications push traditional embedded architectures to their limits. FPGA based hardware acceleration is a potential solution but the programmability gap and time consuming HDL design flow is significant. The proposed research approach to develop “FPGA based programmable hardware acceleration platform” that uses, large number of Streaming Image processing Processors (SIPPro) potentially addresses these issues. SIPPro is pipelined in-order soft-core processor architecture with specific optimisations for image processing applications. Each SIPPro core uses 1 DSP48, 2 Block RAMs and 370 slice-registers, making the processor as compact as possible whilst maintaining flexibility and programmability. It is area efficient, scalable and high performance softcore architecture capable of delivering 530 MIPS per core using Xilinx Zynq SoC (ZC7Z020-3). To evaluate the feasibility of the proposed architecture, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the color and morphology operations accelerated using multiple SIPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 and 33 times for color filtering and morphology operations respectively, with a significant reduced design effort and time.

Effect of high pressure processing in combination with Weissella viridescens as a protective culture against Listeria monocytogenes in ready-to-eat salads of different pH

This study explored the effect of HPP (400 MPa/1 min) and a Weissella viridescens protective culture, alone or in conjunction, against Listeria monocytogenes in ready-to-eat (RTE) salads with different pH values (4.32 and 5.59) during storage at 4 and 12 °C. HPP was able to reduce the counts of the pathogen after treatment achieving approximately a 4.0 and 1.5 log CFU/g reduction in the low and higher pH RTE salad, respectively. However, L. monocytogenes was able to recover and grow during subsequent storage. W. viridescens grew in both RTE salads at both storage temperatures, with HPP resulting in only a small immediate reduction of W. viridescens ranging from 0.50 to 1.2 log CFU/g depending on the pH of the RTE salad. For the lower pH RTE salad, the protective culture was able to gradually reduce the L. monocytogenes counts during storage whereas for the higher pH RTE salad in some cases it delayed growth significantly or exerted a bacteriostatic effect. exerted a bacteriostatic effect. The results revealed that the increased storage temperature led to an increase in the inactivation/inhibition of L. monocytogenes in the presence of W. viridescens. The combination of HPP and W. viridescens is a promising strategy to control L. monocytogenes and can increase safety even when a break in the chill chain occurs.