Can Leakage Models Be More Efficient? Non-Linear Models in Side Channel Attacks

In the last decade, many side channel attacks have been published in academic literature detailing how to efficiently extract secret keys by mounting various attacks, such as differential or correlation power analysis, on cryptosystems. Among the most efficient and widely utilized leakage models involved in these attacks are the Hamming weight and distance models which give a simple, yet effective, approximation of the power consumption for many real-world systems. These leakage models reflect the number of bits switching, which is assumed proportional to the power consumption. However, the actual power consumption changing in the circuits is unlikely to be directly of that form. We, therefore, propose a non-linear leakage model by mapping the existing leakage model via a transform function, by which the changing power consumption is depicted more precisely, hence the attack efficiency can be improved considerably. This has the advantage of utilising a non-linear power model while retaining the simplicity of the Hamming weight or distance models. A modified attack architecture is then suggested to yield the correct key efficiently in practice. Finally, an empirical comparison of the attack results is presented.

Next generation Bridge weigh-in-motion using fibre optic sensors

There have been over 3000 bridge weigh-in-motion (B-WIM) installations in 25 countries worldwide, this has led vast improvements in post processing of B-WIM systems since its introduction in the 1970’s. Existing systems are based on electrical resistance strain gauges which can be prohibitive in achieving data for long term monitoring of rural bridges due to power consumption. This paper introduces a new low-power B-WIM system using fibre optic sensors (FOS). The system consisted of a series of FOS which were attached to the soffit of an existing integral bridge with a single span of 19m. The site selection criteria and full installation process has been detailed in the paper. A method of calibration was adopted using live traffic at the bridge site and based on this calibration the accuracy of the system was determined. New methods of axle detection for B-WIM were investigated and verified in the field.

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

Assessing the Potential for Saving Energy by Impersonating Idle Networked Devices

The idea of proxying network connectivity has been proposed as an efficient mechanism to maintain network presence on behalf of idle devices, so that they can “sleep”. The concept has been around for many years; alternative architectural solutions have been proposed to implement it, which lead to different considerations about capability, effectiveness and energy efficiency. However, there is neither a clear understanding of the potential for energy saving nor a detailed performance comparison among the different proxy architectures. In this paper, we estimate the potential energy saving achievable by different architectural solutions for proxying network connectivity. Our work considers the trade-off between the saving achievable by putting idle devices to sleep and the additional power consumption to run the proxy. Our analysis encompasses a broad range of alternatives, taking into consideration both implementations already available in the market and prototypes built for research purposes. We remark that the main value of our work is the estimation under realistic conditions, taking into consideration power measurements, usage profiles and proxying capabilities.

A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform

Exascale computation is the next target of high performance computing. In the push to create exascale computing platforms, simply increasing the number of hardware devices is not an acceptable option given the limitations of power consumption, heat dissipation, and programming models which are designed for current hardware platforms. Instead, new hardware technologies, coupled with improved programming abstractions and more autonomous runtime systems, are required to achieve this goal. This position paper presents the design of a new runtime for a new heterogeneous hardware platform being developed to explore energy efficient, high performance computing. By combining a number of different technologies, this framework will both simplify the programming of current and future HPC applications, as well as automating the scheduling of data and computation across this new hardware platform. In particular, this work explores the use of FPGAs to achieve both the power and performance goals of exascale, as well as utilising the runtime to automatically effect dynamic configuration and reconfiguration of these platforms. 

NanoStreams: Codesigned Microservers for Edge Analytics in Real Time

NanoStreams explores the design, implementation,and system software stack of micro-servers aimed at processingdata in-situ and in real time. These micro-servers can serve theemerging Edge computing ecosystem, namely the provisioningof advanced computational, storage, and networking capabilitynear data sources to achieve both low latency event processingand high throughput analytical processing, before consideringoff-loading some of this processing to high-capacity datacentres.NanoStreams explores a scale-out micro-server architecture thatcan achieve equivalent QoS to that of conventional rack-mountedservers for high-capacity datacentres, but with dramaticallyreduced form factors and power consumption. To this end,NanoStreams introduces novel solutions in programmable & con-figurable hardware accelerators, as well as the system softwarestack used to access, share, and program those accelerators.Our NanoStreams micro-server prototype has demonstrated 5.5×higher energy-efficiency than a standard Xeon Server. Simulationsof the microserver’s memory system extended to leveragehybrid DDR/NVM main memory indicated 5× higher energyefficiencythan a conventional DDR-based system. 

Multi-Tenant Virtual GPUs for Optimising Performance of a Financial Risk Application

Graphics Processing Units (GPUs) are becoming popular accelerators in modern High-Performance Computing (HPC) clusters. Installing GPUs on each node of the cluster is not efficient resulting in high costs and power consumption as well as underutilisation of the accelerator. The research reported in this paper is motivated towards the use of few physical GPUs by providing cluster nodes access to remote GPUs on-demand for a financial risk application. We hypothesise that sharing GPUs between several nodes, referred to as multi-tenancy, reduces the execution time and energy consumed by an application. Two data transfer modes between the CPU and the GPUs, namely concurrent and sequential, are explored. The key result from the experiments is that multi-tenancy with few physical GPUs using sequential data transfers lowers the execution time and the energy consumed, thereby improving the overall performance of the application.

A Survey on Mobile Anchor Node Assisted Localization in Wireless Sensor Networks

Localization is one of the key technologies in Wireless Sensor Networks (WSNs), since it provides fundamental support for many location-aware protocols and applications. Constraints on cost and power consumption make it infeasible to equip each sensor node in the network with a Global Position System (GPS) unit, especially for large-scale WSNs. A promising method to localize unknown nodes is to use mobile anchor nodes (MANs), which are equipped with GPS units moving among unknown nodes and periodically broadcasting their current locations to help nearby unknown nodes with localization. A considerable body of research has addressed the Mobile Anchor Node Assisted Localization (MANAL) problem. However to the best of our knowledge, no updated surveys on MAAL reflecting recent advances in the field have been presented in the past few years. This survey presents a review of the most successful MANAL algorithms, focusing on the achievements made in the past decade, and aims to become a starting point for researchers who are initiating their endeavors in MANAL research field. In addition, we seek to present a comprehensive review of the recent breakthroughs in the field, providing links to the most interesting and successful advances in this research field.

Performance of downlink massive MIMO in Ricean fading channels with ZF precoder

We investigate the achievable sum rate and energy efficiency of zero-forcing precoded downlink massive multiple-input multiple-output systems in Ricean fading channels. A simple and accurate approximation of the average sum rate is presented, which is valid for a system with arbitrary rank channel means. Based on this expression, the optimal power allocation strategy maximizing the average sum rate is derived. Moreover, considering a general power consumption model, the energy efficiency of the system with rank-1 channel means is characterized. Specifically, the impact of key system parameters, such as the number of users N, the number of BS antennas M, Ricean factor K and the signal-to-noise ratio (SNR) ρ are studied, and closed-form expressions for the optimal ρ and M maximizing the energy efficiency are derived. Our findings show that the optimal power allocation scheme follows the water filling principle, and it can substantially enhance the average sum rate in the presence of strong line-of-sight effect in the low SNR regime. In addition, we demonstrate that the Ricean factor K has significant impact on the optimal values of M, N and ρ.

Circuit-aware design of energy-efficient massive MIMO systems

Densification is a key to greater throughput in cellular networks. The full potential of coordinated multipoint (CoMP) can be realized by massive multiple-input multiple-output (MIMO) systems, where each base station (BS) has very many antennas. However, the improved throughput comes at the price of more infrastructure; hardware cost and circuit power consumption scale linearly/affinely with the number of antennas. In this paper, we show that one can make the circuit power increase with only the square root of the number of antennas by circuit-aware system design. To this end, we derive achievable user rates for a system model with hardware imperfections and show how the level of imperfections can be gradually increased while maintaining high throughput. The connection between this scaling law and the circuit power consumption is established for different circuits at the BS.

Sustainability Enhancement of a Turbine Vane Manufacturing Cell through Digital Simulation based Design

Modern manufacturing systems should satisfy emerging needs related to sustainable development. The design of sustainable manufacturing systems can be valuably supported by simulation, traditionally employed mainly for time and cost reduction. In this paper, a multi-purpose digital simulation approach is proposed to deal with sustainable manufacturing systems design through Discrete Event Simulation (DES) and 3D digital human modelling. DES models integrated with data on power consumption of the manufacturing equipment are utilized to simulate different scenarios with the aim to improve productivity as well as energy efficiency, avoiding resource and energy waste. 3D simulation based on digital human modelling is employed to assess human factors issues related to ergonomics and safety of manufacturing systems. The approach is implemented for the sustainability enhancement of a real manufacturing cell of the aerospace industry, automated by robotic deburring. Alternative scenarios are proposed and simulated, obtaining a significant improvement in terms of energy efficiency (−87%) for the new deburring cell, and a reduction of energy consumption around −69% for the coordinate measuring machine, with high potential annual energy cost savings and increased energy efficiency. Moreover, the simulation-based ergonomic assessment of human operator postures allows 25% improvement of the workcell ergonomic index.

Fruit and vegetable consumption and muscle strength and power during adolescence: a cross-sectional analysis of the Northern Ireland Young Hearts Project 1999-2001

Objectives: To examine the association between fruit and vegetable (FV) consumption and muscle strength and power in an adolescent population. Methods: We conducted a cross-sectional analysis among 1019 boys and 998 girls, aged 12 and 15 years, who participated in The Young Hearts Project. FV consumption (excluding potatoes) was assessed by 7-d diet history. Grip strength and jump power was assessed with a dynamometer and Jump-MD meter, respectively. Associations between FV consumption and strength and power were assessed by regression modelling. Results: Boys and girls with the highest FV intakes (>237.71 g/d and >267.57 g/d, respectively, based on the highest tertile) had significantly higher jump power than those with the lowest intakes (<135.09 g/d and <147.43 g/d, respectively), after adjustment for confounding factors. Although girls with the highest FV intakes had higher grip strength than those with the lowest intakes, no significant independent associations were evident between FV intake and grip strength in boys or girls. Similar findings were observed when FV were analysed separately.Conclusions: Higher FV consumption in this group of adolescents was positively associated with muscle power. There was no independent association between higher FV consumption and muscle strength. Intervention studies are required to determine whether muscle strength and power can be improved through increased FV consumption.

Performance analysis of an improved power-saving medium access protocol for IEEE 802.11 point coordination function WLAN

Wireless enabled portable devices must operate with the highest possible energy efficiency while still maintaining a minimum level and quality of service to meet the user's expectations. The authors analyse the performance of a new pointer-based medium access control protocol that was designed to significantly improve the energy efficiency of user terminals in wireless local area networks. The new protocol, pointer controlled slot allocation and resynchronisation protocol (PCSAR), is based on the existing IEEE 802.11 point coordination function (PCF) standard. PCSAR reduces energy consumption by removing the need for power saving stations to remain awake and listen to the channel. Using OPNET, simulations were performed under symmetric channel loading conditions to compare the performance of PCSAR with the infrastructure power saving mode of IEEE 802.11, PCF-PS. The simulation results demonstrate a significant improvement in energy efficiency without significant reduction in performance when using PCSAR. For a wireless network consisting of an access point and 8 stations in power saving mode, the energy saving was up to 31% while using PCSAR instead of PCF-PS, depending upon frame error rate and load. The results also show that PCSAR offers significantly reduced uplink access delay over PCF-PS while modestly improving uplink throughput.