Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

Juxtaposition and Non-Motion: Varese Bridges Modernism and Electroacoustic Music

Edgard Vare` se’s Poe` me e´ lectronique can be viewed as a bridge between early twentieth-century modernism and electroacoustic music. This connection to early modernism is most clearly seen in its use of musical juxtaposition, a favoured technique of early modernist composers, especially those active in Paris. Juxtaposition and non-motion are considered here, particularly in relationship to Smalley’s exposition of spectromorphology (Smalley 1986), which in its preoccupation with motion omits any significant consideration of non-motion. Juxtaposition and non-motion have an important history within twentieth-century music, and as an early classic of electroacoustic music, Poe` me e´ lectronique is a particularly striking example of a composition that is rich in juxtapositions similar to those found in passages of early modernist music. Examining Poe` me e´ lectronique through the lens of juxtaposition and non-motion reveals how the organisation of its juxtaposed sounds encourages the experience of sound structure suspended time.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.