Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Non-local quantum gates: a cavity-quantum-electrodynamics implementation

The problems related to the management of large quantum registers could be handled in the context of distributed quantum computation: unitary non-local transformations among spatially separated local processors are realized performing local unitary transformations and exchanging classical communication. In this paper, a scheme is proposed for the implementation of universal non-local quantum gates such as a controlled NOT (CNOT) and a controlled quantum phase gate (CQPG). The system chosen for their physical implementation is a cavity-quantum-electrodynamics (CQED) system formed by two spatially separated microwave cavities and two trapped Rydberg atoms. The procedures to follow for the realization of each step necessary to perform a specific non-local operation are described.

Clinical implementation of dynamic multileaf collimation for compensated bladder treatments.

BACKGROUND AND PURPOSE: To describe the clinical implementation of dynamic multileaf collimation (DMLC). Custom compensated four-field treatments of carcinoma of the bladder have been used as a simple test site for the introduction of intensity modulated radiotherapy.MATERIALS AND METHODS: Compensating intensity modulations are calculated from computed tomography (CT) data, accounting for scattered, as well as primary radiation. Modulations are converted to multileaf collimator (MLC) leaf and jaw settings for dynamic delivery on a linear accelerator. A full dose calculation is carried out, accounting for dynamic leaf and jaw motion and transmission through these components. Before treatment, a test run of the delivery is performed and an absolute dose measurement made in a water or solid water phantom. Treatments are verified by in vivo diode measurements and real-time electronic portal imaging. RESULTS: Seven patients have been treated using DMLC. The technique improves dose homogeneity within the target volume, reducing high dose areas and compensating for loss of scatter at the beam edge. A typical total treatment time is 20 min. CONCLUSIONS: Compensated bladder treatments have proven an effective test site for DMLC in an extremely busy clinic.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

An Extended Implementation of the Great Deluge Algorithm for Course Timetabling

Course Scheduling consists of assigning lecture events to a limited set of specific timeslots and rooms. The objective is to satisfy as many soft constraints as possible, while maintaining a feasible solution timetable. The most successful techniques to date require a compute-intensive examination of the solution neighbourhood to direct searches to an optimum solution. Although they may require fewer neighbourhood moves than more exhaustive techniques to gain comparable results, they can take considerably longer to achieve success. This paper introduces an extended version of the Great Deluge Algorithm for the Course Timetabling problem which, while avoiding the problem of getting trapped in local optima, uses simple Neighbourhood search heuristics to obtain solutions in a relatively short amount of time. The paper presents results based on a standard set of benchmark datasets, beating over half of the currently published best results with in some cases up to 60% of an improvement.