Identification of an arsenic tolerant double mutant with a thiol-mediated component and increased arsenic tolerance in phyA mutants

A genetic screen was performed to isolate mutants showing increased arsenic tolerance using an Arabidopsis thaliana population of activation tagged lines. The most arsenic-resistant mutant shows increased arsenate and arsenite tolerance. Genetic analyses of the mutant indicate that the mutant contains two loci that contribute to arsenic tolerance, designated ars4 and ars5. The ars4ars5 double mutant contains a single T-DNA insertion, ars4, which co-segregates with arsenic tolerance and is inserted in the Phytochrome A (PHYA) gene, strongly reducing the expression of PHYA. When grown under far-red light conditions ars4ars5 shows the same elongated hypocotyl phenotype as the previously described strong phyA-211 allele. Three independent phyA alleles, ars4, phyA-211 and a new T-DNA insertion allele (phyA-t) show increased tolerance to arsenate, although to a lesser degree than the ars4ars5 double mutant. Analyses of the ars5 single mutant show that ars5 exhibits stronger arsenic tolerance than ars4, and that ars5 is not linked to ars4. Arsenic tolerance assays with phyB-9 and phot1/phot2 mutants show that these photoreceptor mutants do not exhibit phyA-like arsenic tolerance. Fluorescence HPLC analyses show that elevated levels of phytochelatins were not detected in ars4, ars5 or ars4ars5, however increases in the thiols cysteine, gamma-glutamylcysteine and glutathione were observed. Compared with wild type, the total thiol levels in ars4, ars5 and ars4ars5 mutants were increased up to 80% with combined buthionine sulfoximine and arsenic treatments, suggesting the enhancement of mechanisms that mediate thiol synthesis in the mutants. The presented findings show that PHYA negatively regulates a pathway conferring arsenic tolerance, and that an enhanced thiol synthesis mechanism contributes to the arsenic tolerance of ars4ars5.

FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.

In this paper, the authors have presented one approach to configuring a Wafer-Scale Integration Chip. The approach described is called the 'WINNER', in which bus channels and an external controller for configuring the working processors are not required. In addition, the technique is applicable to high availability systems constructed using conventional methods. The technique can also be extended to arrays of arbitrary size and with any degree of fault tolerance simply by using an appropriate number of cells.