The extracellular vesicles of the helminth pathogen, Fasciola hepatica: biogenesis pathways and cargo molecules involved in parasite pathogenesis.

Extracellular vesicles (EVs) released by parasites have important roles in establishing and maintaining infection. Analysis of the soluble and vesicular secretions of adult Fasciola hepatica has established a definitive characterisation of the total secretome of this zoonotic parasite. Fasciola secretes at least two sub-populations of EVs that differ according to size, cargo molecules and site of release from the parasite. The larger EVs are released from the specialised cells that line the parasite gastrodermus and contain the zymogen of the 37 kDa cathepsin L peptidase that performs a digestive function. The smaller exosome-like vesicle population originate from multivesicular bodies within the tegumental syncytium and carry many previously described immunomodulatory molecules that could be delivered into host cells. By integrating our proteomics data with recently available transcriptomic datasets we have detailed the pathways involved with EV biogenesis in F. hepatica and propose that the small exosome biogenesis occurs via ESCRT-dependent MVB formation in the tegumental syncytium before being shed from the apical plasma membrane. Furthermore, we found that the molecular machinery required for EV biogenesis is constitutively expressed across the intra-mammalian development stages of the parasite. By contrast, the cargo molecules packaged within the EVs are developmentally regulated, most likely to facilitate the parasites migration through host tissue and to counteract host immune attack.

Minimising the Execution of Unknown Bag-of-Task Jobs with Deadlines on the Cloud

Scheduling jobs with deadlines, each of which defines the latest time that a job must be completed, can be challenging on the cloud due to incurred costs and unpredictable performance. This problem is further complicated when there is not enough information to effectively schedule a job such that its deadline is satisfied, and the cost is minimised. In this paper, we present an approach to schedule jobs, whose performance are unknown before execution, with deadlines on the cloud. By performing a sampling phase to collect the necessary information about those jobs, our approach delivers the scheduling decision within 10% cost and 16% violation rate when compared to the ideal setting, which has complete knowledge about each of the jobs from the beginning. It is noted that our proposed algorithm outperforms existing approaches, which use a fixed amount of resources by reducing the violation cost by at least two times.

Lattice-based Encryption Over Standard Lattices in Hardware

Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process. In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations.
Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with lamda_2-bits of precision. Performance results are promising in comparison to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing a stronger security proof; generate 1272 encryptions per second and 4395 decryptions per second.

A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform

Exascale computation is the next target of high performance computing. In the push to create exascale computing platforms, simply increasing the number of hardware devices is not an acceptable option given the limitations of power consumption, heat dissipation, and programming models which are designed for current hardware platforms. Instead, new hardware technologies, coupled with improved programming abstractions and more autonomous runtime systems, are required to achieve this goal. This position paper presents the design of a new runtime for a new heterogeneous hardware platform being developed to explore energy efficient, high performance computing. By combining a number of different technologies, this framework will both simplify the programming of current and future HPC applications, as well as automating the scheduling of data and computation across this new hardware platform. In particular, this work explores the use of FPGAs to achieve both the power and performance goals of exascale, as well as utilising the runtime to automatically effect dynamic configuration and reconfiguration of these platforms. 

PageRank in Malware Categorization

In this paper, we propose a malware categorization method that models malware behavior in terms of instructions using PageRank. PageRank computes ranks of web pages based on structural information and can also compute ranks of instructions that represent the structural information of the instructions in malware analysis methods. Our malware categorization method uses the computed ranks as features in machine learning algorithms. In the evaluation, we compare the effectiveness of different PageRank algorithms and also investigate bagging and boosting algorithms to improve the categorization accuracy.