54 resultados para Arithmetic.


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Jonathan Swift’s Modest Proposal for preventing the children of poor people from being a burthen to their parents or country, and for making them beneficial to the public can be regarded as a critique of consequentialism, perhaps the finest and most effective that has ever been written. Swift’s argument is not explicit but his use of consequentialist reasoning shows how it is possible to rationally justify a course of action which is grotesque and barbaric. This interpretation of Swift’s pamphlet is supported by considering it in relation to works by Bernard Mandeville and William Petty. Both authors employed consequentialist reasoning and Swift is likely to have been familiar with their work.

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The ability of a gold palladium bimetallic catalyst to selectively oxidise toluene has been used to enhance the hydrocarbon selective catalytic reduction of NOx, a reaction in which the interaction of partial oxidation intermediates is considered important. The combination of gold with palladium has a synergistic effect, producing a catalyst that is more active for NOx conversion than the arithmetic sum of the corresponding mono-metallic materials. Three regimes in the conversion profile of the AuPd catalyst are proposed relating to production and consumption of toluene derived species, such as benzaldehyde and benzonitrile. The possible role of these reaction intermediates in the toluene HC-SCR reaction is examined. Using 15NO, the formation of N2 and N2O is observed via the direct interaction between the nitrogen atom of benzonitrile and 15NO. The higher activity of the bimetallic catalyst for the NOx reduction reaction by toluene is discussed in the context of these partial oxidation intermediates.

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The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.

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The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

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Jonathan Swift wrote perceptively about the emerging commercial society
in Britain in the early eighteenth century. His particular focus was on the
financial revolution and its implications for economic and political stability
as well as for shifts of power between the landed and commercial
classes. Following his return to Ireland Swift’s focus shifted to the developmental
problems of his native country. In several pamphlets he advocated
consumption of domestic products, challenged existing political
structures and made trenchant criticisms of absenteeism and other dysfunctional
aspects of the land tenure system. Swift’s politico-economic
concerns are fully reflected in his best known work, Gulliver’s Travels but
his most pointed criticism of the emerging commercial system is contained
in A Modest Proposal. Written in the form of an economic pamphlet, A
Modest Proposal is ostensibly designed to address the problem of poverty
in Ireland. In addition to its implicit criticism of economic policy in Ireland,
the pamphlet challenges the separation of economics and morality as
evidenced in the writings of William Petty and Bernard Mandeville. Swift
parodies Petty’s political arithmetic but it is suggested here that he also
had in his sights the consequentialist reasoning present in the work of
both authors but explicitly so in Mandeville.
Keywords: financial revolution, public debt, paper credit, rationality, political
arithmetic, consequentialism, Petty (William), Mandeville (Bernard)

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Power has become a key constraint in current nanoscale integrated circuit design due to the increasing demands for mobile computing and a low carbon economy. As an emerging technology, an inexact circuit design offers a promising approach to significantly reduce both dynamic and static power dissipation for error tolerant applications. Although fixed-point arithmetic circuits have been studied in terms of inexact computing, floating-point arithmetic circuits have not been fully considered although require more power. In this paper, the first inexact floating-point adder is designed and applied to high dynamic range (HDR) image processing. Inexact floating-point adders are proposed by approximately designing an exponent subtractor and mantissa adder. Related logic operations including normalization and rounding modules are also considered in terms of inexact computing. Two HDR images are processed using the proposed inexact floating-point adders to show the validity of the inexact design. HDR-VDP is used as a metric to measure the subjective results of the image addition. Significant improvements have been achieved in terms of area, delay and power consumption. Comparison results show that the proposed inexact floating-point adders can improve power consumption and the power-delay product by 29.98% and 39.60%, respectively.

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Quantum-dot cellular automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. However, how to properly evaluate the QCA circuits has not been carefully considered. To date, metrics and area-delay cost functions directly mapped from CMOS technology have been used to compare QCA designs, which is inappropriate due to the differences between these two technologies. In this paper, several cost metrics specifically aimed at QCA circuits are studied. It is found that delay, the number of QCA logic gates, and the number and type of crossovers, are important metrics that should be considered when comparing QCA designs. A family of new cost functions for QCA circuits is proposed. As fundamental components in QCA computing arithmetic, QCA adders are reviewed and evaluated with the proposed cost functions. By taking the new cost metrics into account, previous best adders become unattractive and it has been shown that different optimization goals lead to different “best” adders.

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Applications that cannot tolerate the loss of accuracy that results from binary arithmetic demand hardware decimal arithmetic designs. Binary arithmetic in Quantum-dot cellular automata (QCA) technology has been extensively investigated in recent years. However, only limited attention has been paid to QCA decimal arithmetic. In this paper, two cost-efficient binary-coded decimal (BCD) adders are presented. One is based on the carry flow adder (CFA) using a conventional correction method. The other uses the carry look ahead (CLA) algorithm which is the first QCA CLA decimal adder proposed to date. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The proposed CFA-based BCD adder has the smallest area with the least number of cells. The proposed CLA-based BCD adder is the fastest with an increase in speed of over 60% when compared with the previous fastest decimal QCA adder. It also has the lowest overall cost with a reduction of over 90% when compared with the previous most cost-efficient design.

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Solving microkinetics of catalytic systems, which bridges microscopic processes and macroscopic reaction rates, is currently vital for understanding catalysis in silico. However, traditional microkinetic solvers possess several drawbacks that make the process slow and unreliable for complicated catalytic systems. In this paper, a new approach, the so-called reversibility iteration method (RIM), is developed to solve microkinetics for catalytic systems. Using the chemical potential notation we previously proposed to simplify the kinetic framework, the catalytic systems can be analytically illustrated to be logically equivalent to the electric circuit, and the reaction rate and coverage can be calculated by updating the values of reversibilities. Compared to the traditional modified Newton iteration method (NIM), our method is not sensitive to the initial guess of the solution and typically requires fewer iteration steps. Moreover, the method does not require arbitrary-precision arithmetic and has a higher probability of successfully solving the system. These features make it ∼1000 times faster than the modified Newton iteration method for the systems we tested. Moreover, the derived concept and the mathematical framework presented in this work may provide new insight into catalytic reaction networks.