A Measurements Based Comparison of New and Classical Models Used to Characterize Fading in Body Area Networks

In this paper we compare a number of the classical models used to characterize fading in body area networks (BANs) with the recently proposed shadowed ț–ȝ fading model. In particular, we focus on BAN channels which are considered to be susceptible to shadowing by the human body. The measurements considered in this study were conducted at 2.45 GHz for hypothetical BAN channels operating in both anechoic and highly reverberant environments while the person was moving. Compared to the Rice, Nakagami and lognormal fading models, it was found that the recently proposed shadowed ț௅μ fading model provided an enhanced fit to the measured data.

Histogram of oriented gradients front end processing: An FPGA based processor approach

The Field Programmable Gate Array (FPGA) implementation of the commonly used Histogram of Oriented Gradients (HOG) algorithm is explored. The HOG algorithm is employed to extract features for object detection. A key focus has been to explore the use of a new FPGA-based processor which has been targeted at image processing. The paper gives details of the mapping and scheduling factors that influence the performance and the stages that were undertaken to allow the algorithm to be deployed on FPGA hardware, whilst taking into account the specific IPPro architecture features. We show that multi-core IPPro performance can exceed that of against state-of-the-art FPGA designs by up to 3.2 times with reduced design and implementation effort and increased flexibility all on a low cost, Zynq programmable system.

Accelerating integer-based fully homomorphic encryption using Comba multiplication

Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.

Free Improvisation in Europe:Lecture and Hands-on Workshop, given at 5 different universities in Brazil during February - June 2014

The lecture traces the beginnings of the free improvisation scene in Europe, commencing in the 1960. I present a multitude of video and audio examples of some of the most prominent improvisers of the time.
I focus specifically on the scene that developed around John Stevens and his SME (Spontaneous Music Ensemble). The work of Derek Bailey, specifically his writings in “Improvisation: its nature and practice in music” (1980), will feature.

The practical workshop invites improvisers (beginners to advanced with any instruments) to work with me on several listening and improvisation exercises.
Many of the exercises will be based on the innovative methods as developed by John Stevens in his work “Search and Reflect”. Participants will be able to experiment with a few essential ‘sound/listening’ exercises, guided by myself.
It is envisaged that a small ensemble is formed which will explore several improvisatory strategies. This part is open to all skill levels, all ages and any instrumental groupings.

Gait period estimation algorithm based on the angles of extremities

Gait period estimation is an important step in the gait recognition framework. In this paper, we propose a new gait cycle detection method based on the angles of extreme points of both legs. In addition to that, to further improve the estimation of the gait period, the proposed algorithm divides the gait sequence into sections before identifying the maximum values. The proposed algorithm is scale invariant and less dependent on the silhouette shape. The performance of the proposed method was evaluated using the OU-ISIR speed variation gait database. The experimental results show that the proposed method achieved 90.2% gait recognition accuracy and outperforms previous methods found in the literature with the second best only achieved 67.65% accuracy.

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.

FPGA-based Tabu Search for Detection in Large-Scale MIMO Systems

The increasing scale of Multiple-Input Multiple- Output (MIMO) topologies employed in forthcoming wireless communications standards presents a substantial implementation challenge to designers of embedded baseband signal processing architectures for MIMO transceivers. Specifically the increased scale of such systems has a substantial impact on the perfor- mance/cost balance of detection algorithms for these systems. Whilst in small-scale systems Sphere Decoding (SD) algorithms offer the best quasi-ML performance/cost balance, in larger systems heuristic detectors, such Tabu-Search (TS) detectors are superior. This paper addresses a dearth of research in architectures for TS-based MIMO detection, presenting the first known realisations of TS detectors for 4 × 4 and 10 × 10 MIMO systems. To the best of the authors’ knowledge, these are the largest single-chip detectors on record.