Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

Hierarchical Video Summarization in Reference Subspace

In this paper, a hierarchical video structure summarization approach using Laplacian Eigenmap is proposed, where a small set of reference frames is selected from the video sequence to form a reference subspace to measure the dissimilarity between two arbitrary frames. In the proposed summarization scheme, the shot-level key frames are first detected from the continuity of inter-frame dissimilarity, and the sub-shot level and scene level representative frames are then summarized by using K-mean clustering. The experiment is carried on both test videos and movies, and the results show that in comparison with a similar approach using latent semantic analysis, the proposed approach using Laplacian Eigenmap can achieve a better recall rate in keyframe detection, and gives an efficient hierarchical summarization at sub shot, shot and scene levels subsequently.

A bargaining set for monotonic simple games based on external and internal stability

A new bargaining set based on notions of both internal and external stability is developed in the context of endogenous coalition formation. It allows to make an explicit distinction between within-group and outside-group deviation options. This type of distinction is not present in current bargaining sets. For the class of monotonic proper simple games, the outcomes in the bargaining set are characterized. Furthermore, it is shown that the bargaining set of any homogeneous weighted majority game contains an outcome for which the underlying coalition structure consists of a minimal winning coalition and its complement.

Coalitional Games and Contracts Based on Individual Deviations

We study what coalitions form and how the members of each coalition split the coalition value in coalitional games in which only individual deviations are allowed. In this context we employ three stability notions: individual, contractual, and compensational stability. These notions differ in terms of the underlying contractual assumptions. We characterize the coalitional games in which individually stable outcomes exist by means of the top-partition property. Furthermore, we show that any coalition structure of maximum social worth is both contractually and compensationally stable.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.