A Wavelet-Prony Method for Modeling of Fixed-Speed Wind Farm Low-Frequency Power Pulsations

The increasing penetration of wind generation on the Island of Ireland has been accompanied by close investigation of low-frequency pulsations contained within active power flow. A primary concern is excitation of low-frequency oscillation modes already present on the system, particularly the 0.75 Hz mode as a consequence of interconnection between the Northern and Southern power system networks. In order to determine whether the prevalence of wind generation has a negative effect (excites modes) or positive impact (damping of modes) on the power system, oscillations must be measured and characterised. Using time – frequency methods, this paper presents work that has been conducted to extract features from low-frequency active power pulsations to determine the composition of oscillatory modes which may impact on dynamic stability. The paper proposes a combined wavelet-Prony method to extract modal components and determine damping factors. The method is exemplified using real data obtained from wind farm measurements.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.