ArchiBabel: Tracing the Writing Architecture Project in Architectural Education

Though much recent scholarship has investigated the potential of writing in creative practice (including visual arts, drama, even choreography), there are few models in the literature which discuss writing in the context of architectural education. The paper presented here aims to address this dearth of pedagogical research, analysing the cross-disciplinary Writing Architecture Project based in the undergraduate course of the School of Architecture at QUB. Over the course of four years, teaching staff, in partnership with the university's Learning Development Service, technicians and specialist librarians, have addressed an unfortunately persistent struggle for both architecture students and professionals alike to research and construct argument in written form. The paper examines the current problem as identified in the literature before analysing the efficacy of the variety of teaching methods used in the Writing Architecture Project, with conclusions about the project’s success and continuing challenges.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Resource utilization and cost analyses of home-based palliative care service provision:The Niagara West End-of-Life Shared-Care Project

Background: Increasing emphasis is being placed on the economics of health care service delivery - including home-based palliative care. Aim: This paper analyzes resource utilization and costs of a shared-care demonstration project in rural Ontario (Canada) from the public health care system's perspective. Design: To provide enhanced end-of-life care, the shared-care approach ensured exchange of expertise and knowledge and coordination of services in line with the understood goals of care. Resource utilization and costs were tracked over the 15 month study period from January 2005 to March 2006. Results: Of the 95 study participants (average age 71 years), 83 had a cancer diagnosis (87%); the non-cancer diagnoses (12 patients, 13%) included mainly advanced heart diseases and COPD. Community Care Access Centre and Enhanced Palliative Care Team-based homemaking and specialized nursing services were the most frequented offerings, followed by equipment/transportation services and palliative care consults for pain and symptom management. Total costs for all patient-related services (in 2007 CAN) were 1,625,658.07 - or 17,112.19 per patient/117.95 per patient day. Conclusion: While higher than expenditures previously reported for a cancer-only population in an urban Ontario setting, the costs were still within the parameters of the US Medicare Hospice Benefits, on a par with the per diem funding assigned for long-term care homes and lower than both average alternate level of care and hospital costs within the Province of Ontario. The study results may assist service planners in the appropriate allocation of resources and service packaging to meet the complex needs of palliative care populations. © 2012 The Author(s).

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

In this paper, we have developed a low-complexity algorithm for epileptic seizure detection with a high degree of accuracy. The algorithm has been designed to be feasibly implementable as battery-powered low-power implantable epileptic seizure detection system or epilepsy prosthesis. This is achieved by utilizing design optimization techniques at different levels of abstraction. Particularly, user-specific critical parameters are identified at the algorithmic level and are explicitly used along with multiplier-less implementations at the architecture level. The system has been tested on neural data obtained from in-vivo animal recordings and has been implemented in 90nm bulk-Si technology. The results show up to 90 % savings in power as compared to prevalent wavelet based seizure detection technique while achieving 97% average detection rate. Copyright 2010 ACM.

FPGA based Streaming Image Processing Processor (SIPPro) architecture to accelerate data intensive applications

Current data-intensive image processing applications push traditional embedded architectures to their limits. FPGA based hardware acceleration is a potential solution but the programmability gap and time consuming HDL design flow is significant. The proposed research approach to develop “FPGA based programmable hardware acceleration platform” that uses, large number of Streaming Image processing Processors (SIPPro) potentially addresses these issues. SIPPro is pipelined in-order soft-core processor architecture with specific optimisations for image processing applications. Each SIPPro core uses 1 DSP48, 2 Block RAMs and 370 slice-registers, making the processor as compact as possible whilst maintaining flexibility and programmability. It is area efficient, scalable and high performance softcore architecture capable of delivering 530 MIPS per core using Xilinx Zynq SoC (ZC7Z020-3). To evaluate the feasibility of the proposed architecture, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the color and morphology operations accelerated using multiple SIPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 and 33 times for color filtering and morphology operations respectively, with a significant reduced design effort and time.

Inexact-aware architecture design for ultra-low power bio-signal analysis

This study introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimise energy consumption. In this scenario, the reliability of static RAM (SRAM) memories cannot be guaranteed when using conventional 6-transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near-threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, the authors propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e. their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. The authors illustrate their scheme on an industrial benchmark application performing the power spectrum analysis of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.