Effect of chronic angiotensin converting enzyme inhibition on spatial memory and anxiety-like behavours in rats

Angiotensin converting enzyme inhibitors (ACEis) are widely used anti-hypertensive agents that are also reported to have positive effects on mood and cognition. The present study examined the influence of the ACEi, perindopril, on cognitive performance and anxiety measures in rats. Two groups of rats were treated orally for one week with the ACEi, perindopril, at doses of 0.1 and 1.0mg/kg/day. Learning was assessed by the reference memory task in the water maze, comparing treated to control rats. Over five training days both perindopril-treated groups learnt the location of the submerged platform in the water maze task significantly faster than control rats. A 60s probe trial on day 6 showed that the 1.0mg/kg/day group spent significantly longer time in the training quadrant than control rats. This improved performance in the swim maze task was not due to the effect of perindopril on motor activity or the anxiety levels of the rats as perindopril-treated and control animals behaved similarly in activity boxes and on the elevated+maze. These results confirm the anecdotal human studies that ACEis have a positive influence on cognition and provide possibilities for ACEis to be developed into therapies for memory loss.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.