Image processing chip for small object detection

A new, front-end image processing chip is presented for real-time small object detection. It has been implemented using a 0.6 µ, 3.3 V CMOS technology and operates on 10-bit input data at 54 megasamples per second. It occupies an area of 12.9 mm×13.6 mm (including pads), dissipates 1.5 W, has 92 I/O pins and is to be housed in a 160-pin ceramic quarter flat-pack. It performs both one- and two-dimensional FIR filtering and a multilayer perceptron (MLP) neural network function using a reconfigurable array of 21 multiplication-accumulation cells which corresponds to a window size of 7×3. The chip can cope with images of 2047 pixels per line and can be cascaded to cope with larger window sizes. The chip performs two billion fixed point multiplications and additions per second.

A Low Complexity Real-time MIMO-Preprocessing For Fixed Complexity Sphere Decoder

Modern Multiple-Input Multiple-Output (MIMO) communication systems place huge demands on embedded processing resources in terms of throughput, latency and resource utilization. State-of-the-art MIMO detector algorithms, such as Fixed-Complexity Sphere Decoding (FSD), rely on efficient channel preprocessing involving numerous calculations of the pseudo-inverse of the channel matrix by QR Decomposition (QRD) and ordering. These highly complicated operations can quickly become the critical prerequisite for real-time MIMO detection, exaggerated as the number of antennas in a MIMO detector increases. This paper describes a sorted QR decomposition (SQRD) algorithm extended for FSD, which significantly reduces the complexity and latency
of this preprocessing step and increases the throughput of MIMO detection. It merges the calculations of the QRD and ordering operations to avoid multiple iterations of QRD. Specifically, it shows that SQRD reduces the computational complexity by over 60-70% when compared to conventional
MIMO preprocessing algorithms. In 4x4 to 7x7 MIMO cases, the approach suffers merely 0.16-0.2 dB reduction in Bit Error Rate (BER) performance.

1D-Leaky Wave Antenna Employing Parallel-Plate Waveguide Loaded With PRS and HIS

A new type of one-dimensional leaky-wave antenna (LWA) with independent control of the beam-pointing angle and beamwidth is presented. The antenna is based on a simple structure composed of a bulk parallel-plate waveguide (PPW) loaded with two printed circuit boards (PCBs), each one consisting of an array of printed dipoles. One PCB acts as a partially reflective surface (PRS), and the other grounded PCB behaves as a high impedance surface (HIS). It is shown that an independent control of the leaky-mode phase and leakage rate can be achieved by changing the lengths of the PRS and HIS dipoles, thus resulting in a flexible adjustment of the LWA pointing direction and directivity. The leaky-mode dispersion curves are obtained with a simple Transverse Equivalent Network (TEN), and they are validated with three-dimensional full-wave simulations. Experimental results on fabricated prototypes operating at 15 GHz are reported, demonstrating the versatile and independent control of the LWA performance by changing the PRS and HIS parameters.