Perturbed frequency-selective surfaces fabricated on large thin polymer membranes for multiband infrared applications

The design, fabrication, and characterization of single-screen perturbed frequency-selective surfaces (FSS) at infrared frequencies for single and multiband applications are reported. Single-band FSS based on parallel strips have been perturbed by decreasing the length of every second strip within the array in order to achieve dual band-stop responses. The same principle has been extended to design FSS exhibiting tri- and quadreflection bands. In addition, strip FSSs have been perturbed by replacing every second strip for a metallic ring, resulting in dual-band filters with different polarization responses of the bands. These designs have been fabricated on large thin polyimide membranes using sacrificial silicon wafers. An oxide interlayer between the sacrificial silicon wafer and the polyimide membrane is employed to stop the silicon etching and is wet etched subsequently by a solution of ammonium fluoride and acetic acid that does not attack either the polyimide membrane or the aluminium FSS elements. Fourier transform infrared spectroscopy measurements are presented to validate the predicted responses of the fabricated prototypes.

Kinematic modeling of Exechon parallel kinematic machine

The studies on PKMs have attracted a great attention to robotics community. By deploying a parallel kinematic structure, a parallel kinematic machine (PKM) is expected to possess the advantages of heavier working load, higher speed, and higher precision. Hundreds of new PKMs have been proposed. However, due to the considerable gaps between the desired and actual performances, the majorities of the developed PKMs were the prototypes in research laboratories and only a few of them have been practically applied for various applications; among the successful PKMs, the Exechon machine tool is recently developed. The Exechon adopts unique over-constrained structure, and it has been improved based on the success of the Tricept parallel kinematic machine. Note that the quantifiable theoretical studies have yet been conducted to validate its superior performances, and its kinematic model is not publically available. In this paper, the kinematic characteristics of this new machine tool is investigated, the concise models of forward and inverse kinematics have been developed. These models can be used to evaluate the performances of an existing Exechon machine tool and to optimize new structures of an Exechon machine to accomplish some specific tasks.

Comparison of parallel and perpendicular polarized counterpropagating light for suppressing high harmonic generation

The use of counterpropagating laser pulses to suppress high harmonic generation (HHG) is investigated experimentally for pulses polarized parallel or perpendicular to the driving laser pulse. It is shown for the first time that perpendicularly polarized pulses can suppress HHG. The intensity of the counterpropagating pulse required for harmonic suppression is found to be much larger for perpendicular polarization than for parallel polarization, in good agreement with simple models of the harmonic suppression. These results have applications to quasi-phase-matching of HHG with trains of counterpropagating pulses. (C) 2007 Optical Society of America.

A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.

Parallel Programming of General-Purpose Programs Using Task-Based Programming Models

The prevalence of multicore processors is bound to drive most kinds of software development towards parallel programming. To limit the difficulty and overhead of parallel software design and maintenance, it is crucial that parallel programming models allow an easy-to-understand, concise and dense representation of parallelism. Parallel programming models such as Cilk++ and Intel TBBs attempt to offer a better, higher-level abstraction for parallel programming than threads and locking synchronization. It is not straightforward, however, to express all patterns of parallelism in these models. Pipelines are an important parallel construct, although difficult to express in Cilk and TBBs in a straightfor- ward way, not without a verbose restructuring of the code. In this paper we demonstrate that pipeline parallelism can be easily and concisely expressed in a Cilk-like language, which we extend with input, output and input/output dependency types on procedure arguments, enforced at runtime by the scheduler. We evaluate our implementation on real applications and show that our Cilk-like scheduler, extended to track and enforce these dependencies has performance comparable to Cilk++.

Formal Analysis of MPI-based Parallel Programs

Most parallel computing applications in highperformance computing use the Message Passing Interface (MPI) API. Given the fundamental importance of parallel computing to science and engineering research, application correctness is paramount. MPI was originally developed around 1993 by the MPI Forum, a group of vendors, parallel programming researchers, and computational scientists. However, the document defining the standard is not issued by an official standards organization but has become a de facto standard © 2011 ACM.

Structured data access annotations for massively parallel computations

We describe an approach aimed at addressing the issue of joint exploitation of control (stream) and data parallelism in a skeleton based parallel programming environment, based on annotations and refactoring. Annotations drive efficient implementation of a parallel computation. Refactoring is used to transform the associated skeleton tree into a more efficient, functionally equivalent skeleton tree. In most cases, cost models are used to drive the refactoring process. We show how sample use case applications/kernels may be optimized and discuss preliminary experiments with FastFlow assessing the theoretical results. © 2013 Springer-Verlag.

The ParaPhrase Project:Parallel patterns for adaptive heterogeneous multicore systems

This paper describes the ParaPhrase project, a new 3-year targeted research project funded under EU Framework 7 Objective 3.4 (Computer Systems), starting in October 2011. ParaPhrase aims to follow a new approach to introducing parallelism using advanced refactoring techniques coupled with high-level parallel design patterns. The refactoring approach will use these design patterns to restructure programs defined as networks of software components into other forms that are more suited to parallel execution. The programmer will be aided by high-level cost information that will be integrated into the refactoring tools. The implementation of these patterns will then use a well-understood algorithmic skeleton approach to achieve good parallelism. A key ParaPhrase design goal is that parallel components are intended to match heterogeneous architectures, defined in terms of CPU/GPU combinations, for example. In order to achieve this, the ParaPhrase approach will map components at link time to the available hardware, and will then re-map them during program execution, taking account of multiple applications, changes in hardware resource availability, the desire to reduce communication costs etc. In this way, we aim to develop a new approach to programming that will be able to produce software that can adapt to dynamic changes in the system environment. Moreover, by using a strong component basis for parallelism, we can achieve potentially significant gains in terms of reducing sharing at a high level of abstraction, and so in reducing or even eliminating the costs that are usually associated with cache management, locking, and synchronisation. © 2013 Springer-Verlag Berlin Heidelberg.