VEDA:Variation-aware energy-efficient discrete Wavelet Transform architecture

In this paper, we present a unified approach to an energy-efficient variation-tolerant design of Discrete Wavelet Transform (DWT) in the context of image processing applications. It is to be noted that it is not necessary to produce exactly correct numerical outputs in most image processing applications. We exploit this important feature and propose a design methodology for DWT which shows energy quality tradeoffs at each level of design hierarchy starting from the algorithm level down to the architecture and circuit levels by taking advantage of the limited perceptual ability of the Human Visual System. A unique feature of this design methodology is that it guarantees robustness under process variability and facilitates aggressive voltage over-scaling. Simulation results show significant energy savings (74% - 83%) with minor degradations in output image quality and avert catastrophic failures under process variations compared to a conventional design. © 2010 IEEE.

Significance Driven Computation on Next-Generation Unreliable Platforms

In this paper, we propose a design paradigm for energy efficient and variation-aware operation of next-generation multicore heterogeneous platforms. The main idea behind the proposed approach lies on the observation that not all operations are equally important in shaping the output quality of various applications and of the overall system. Based on such an observation, we suggest that all levels of the software design stack, including the programming model, compiler, operating system (OS) and run-time system should identify the critical tasks and ensure correct operation of such tasks by assigning them to dynamically adjusted reliable cores/units. Specifically, based on error rates and operating conditions identified by a sense-and-adapt (SeA) unit, the OS selects and sets the right mode of operation of the overall system. The run-time system identifies the critical/less-critical tasks based on special directives and schedules them to the appropriate units that are dynamically adjusted for highly-accurate/approximate operation by tuning their voltage/frequency. Units that execute less significant operations can operate at voltages less than what is required for correct operation and consume less power, if required, since such tasks do not need to be always exact as opposed to the critical ones. Such scheme can lead to energy efficient and reliable operation, while reducing the design cost and overheads of conventional circuit/micro-architecture level techniques.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

The role of the relative voltage and phase for frequency coupling in a dual-frequency capacitively coupled plasma

Frequency coupling in multifrequency discharges is a complex nonlinear interaction of the different frequency components. An alpha-mode low pressure rf capacitively coupled plasma operated simultaneously with two frequencies is investigated and the coupling of the two frequencies is observed to greatly influence the excitation and ionization within the discharge. Through this, plasma production and sustainment are dictated by the corresponding electron dynamics and can be manipulated through the dual-frequency sheath. These mechanisms are influenced by the relative voltage and also the relative phase of the two frequencies.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

High-efficiency low-voltage-stress Class-EF PA with extended maximum operating frequency

The Class-EF power amplifier (PA) introduced recently has a peak switch voltage much lower than the well-known Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. As a result, softswitching operation that minimizes power dissipation during OFF-to-ON transient cannot be achieved at high frequencies. A novel Class-EF topology with transmission-line load network proposed in this paper allows the PA to operate at much higher frequencies without trading the other figures of merit. Closed-form formulations are derived to simultaneously satisfy the Class-EF impedances requirement at fundamental frequency, all even harmonics, and the first two odd harmonics as well as to provide matching to 50O load. © 2011 Institut fur Mikrowellen.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Achievable rates and outage probability of cognitive radio with dynamic frequency hopping under imperfect spectrum sensing

In this study, the authors propose simple methods to evaluate the achievable rates and outage probability of a cognitive radio (CR) link that takes into account the imperfectness of spectrum sensing. In the considered system, the CR transmitter and receiver correlatively sense and dynamically exploit the spectrum pool via dynamic frequency hopping. Under imperfect spectrum sensing, false-alarm and miss-detection occur which cause impulsive interference emerged from collisions due to the simultaneous spectrum access of primary and cognitive users. That makes it very challenging to evaluate the achievable rates. By first examining the static link where the channel is assumed to be constant over time, they show that the achievable rate using a Gaussian input can be calculated accurately through a simple series representation. In the second part of this study, they extend the calculation of the achievable rate to wireless fading environments. To take into account the effect of fading, they introduce a piece-wise linear curve fitting-based method to approximate the instantaneous achievable rate curve as a combination of linear segments. It is then demonstrated that the ergodic achievable rate in fast fading and the outage probability in slow fading can be calculated to achieve any given accuracy level.

Oxaliplatin induces hyperexcitability at motor and autonomic neuromuscular junctions through effects on voltage-gated sodium channels

Oxaliplatin, an effective cytotoxic treatment in combination with 5-fluorouracil for colorectal cancer, is associated with sensory, motor and autonomic neurotoxicity. Motor symptoms include hyperexcitability while autonomic effects include urinary retention, but the cause of these side-effects is unknown. We examined the effects on motor nerve function in the mouse hemidiaphragm and on the autonomic system in the vas deferens. In the mouse diaphragm, oxaliplatin (0.5 mM) induced multiple endplate potentials (EPPs) following a single stimulus, and was associated with an increase in spontaneous miniature EPP frequency. In the vas deferens, spontaneous excitatory junction potential frequency was increased after 30 min exposure to oxaliplatin; no changes in resting Ca(2+) concentration in nerve terminal varicosities were observed, and recovery after stimuli trains was unaffected.In both tissues, an oxaliplatin-induced increase in spontaneous activity was prevented by the voltage-gated Na(+) channel blocker tetrodotoxin (TTX). Carbamazepine (0.3 mM) also prevented multiple EPPs and the increase in spontaneous activity in both tissues. In diaphragm, beta-pompilidotoxin (100 microM), which slows Na(+) channel inactivation, induced multiple EPPs similar to oxaliplatin's effect. By contrast, blockers of K(+) channels (4-aminopyridine and apamin) did not replicate oxaliplatin-induced hyperexcitability in the diaphragm. The prevention of hyperexcitability by TTX blockade implies that oxaliplatin acts on nerve conduction rather than by effecting repolarisation. The similarity between beta-pompilidotoxin and oxaliplatin suggests that alteration of voltage-gated Na(+) channel kinetics is likely to underlie the acute neurotoxic actions of oxaliplatin.

Single-ionization of helium at Ti:sapphire wavelengths: rates and scaling laws

We present a numerical and theoretical study of intense-field single-electron ionization of helium at 390 nm and 780 nm. Accurate ionization rates (over an intensity range of (0.175-34) X10^14 W/ cm^2 at 390 nm, and (0.275 - 14.4) X 10^14 W /cm^2 at 780 nm) are obtained from full-dimensionality integrations of the time-dependent helium-laser Schroedinger equation. We show that the power law of lowest order perturbation theory, modified with a ponderomotive-shifted ionization potential, is capable of modelling the ionization rates over an intensity range that extends up to two orders of magnitude higher than that applicable to perturbation theory alone. Writing the modified perturbation theory in terms of scaled wavelength and intensity variables, we obtain to first approximation a single ionization law for both the 390 nm and 780 nm cases. To model the data in the high intensity limit as well as in the low, a new function is introduced for the rate. This function has, in part, a resemblance to that derived from tunnelling theory but, importantly, retains the correct frequency-dependence and scaling behaviour derived from the perturbative-like models at lower intensities. Comparison with the predictions of classical ADK tunnelling theory confirms that ADK performs poorly in the frequency and intensity domain treated here.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.