A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Harnessing naturally randomized transcription to infer regulatory relationships among genes

We develop an approach utilizing randomized genotypes to rigorously infer causal regulatory relationships among genes at the transcriptional level, based on experiments in which genotyping and expression profiling are performed. This approach can be used to build transcriptional regulatory networks and to identify putative regulators of genes. We apply the method to an experiment in yeast, in which genes known to be in the same processes and functions are recovered in the resulting transcriptional regulatory network.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

Ginkgolide B and bilobalide block the pore of the 5-HT3 receptor at a location that overlaps the picrotoxin binding site

Extracts from the Ginkgo biloba tree are widely used as herbal medicines, and include bilobalide (BB) and ginkgolides A and B (GA and GB). Here we examine their effects on human 5-HT(3)A and 5-HT(3)AB receptors, and compare these to the effects of the structurally related compounds picrotin (PTN) and picrotoxinin (PXN), the two components of picrotoxin (PTX), a known channel blocker of 5-HT3, nACh and GABA(A) receptors. The compounds inhibited 5-HT-induced responses of 5-HT3 receptors expressed in Xenopus oocytes, with IC50 values of 470 mu M (BB), 730 mu M (GB), 470 mu M (PTN), 11 mu M (PXN) and > 1 mM (GA) in 5-HT(3)A receptors, and 3.1 mM (BB), 3.9 mM (GB), 2.7 mM (PTN), 62 mu M (PXN) and > 1 mM (GA) in 5-HT(3)AB receptors. Radioligand binding on receptors expressed in HEK 293 cells showed none of the compounds displaced the specific 5-HT3 receptor antagonist [H-3]granisetron, confirming that they do not act at the agonist binding site. Inhibition by GB at 5-HT(3)A receptors is weakly use-dependent, and recovery is activity dependent, indicating channel block. To further probe their site of action at 5-HT(3)A receptors, BB and GB were applied alone or in combination with PXN, and the results fitted to a mathematical model; the data revealed partially overlapping sites of action. We conclude that BB and GB block the channel of the 5-HT(3)A receptor. Thus these compounds have comparable, although less potent, behaviour than at some other Cys-loop receptors, demonstrating their actions are conserved across the family. (C) 2010 Published by Elsevier Ltd.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Ultrafast Low-Loss 40-70 GHz SPST Switch

The design and characterizations of an ultrafast single-pole single-throw (SPST) absorptive differential switch are presented. The switch exhibits low insertion loss less than 1 dB, and isolation better than 16 dB from 40 to 70 GHz. Sub-nanosecond switching time is achieved by adopting a differential current-steering technique. The total measured rise and fall time are 75 ps envisaging that switching rates up to 13 Gb/s are achievable. To our best knowledge, this is the fastest, lowest insertion loss V-band SPST switch yet reported that can operate over a wide bandwidth of 30 GHz.