Randomised controlled trial of home-based walking programmes at and below current recommended levels of exercise in sedentary adults

Objectives: To determine, using unsupervised walking programmes, the effects of exercise at a level lower than currently recommended to improve cardiovascular risk factors and functional capacity.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

The evolution of the UK charity Statement of Recommended Practice: The influence of key stakeholders

In the early 1980s, a landmark study identified significant poor reporting practice in UK charities. As a consequence, a journey was commenced with the aim of improving accounting and reporting as a basis for enhancing accountability by charities. Much of this change has been effected through the publication of evolving Statements of Recommended Practice (SORPs) on accounting and reporting by charities. This paper analyses the evolution of the SORP through time using insights from stakeholder theory, and argues that the key stakeholders influencing the evolving SORP have been government and the accounting profession.