FPGA Implementations of the Round Two SHA-3 Candidates

The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first work to date to present hardware designs which test for all message digest sizes (224, 256, 384, 512), and also the only work to include the padding as part of the hardware for the SHA-3 hash functions.

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

Generic low-latency NoC router architecture for FPGA computing systems

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems. © 2011 IEEE.

Simultaneously multiply-configurable or superposed molecular logic systems composed of ICT (internal charge transfer) chromophores and fluorophores integrated with one- or two-ion receptors

Integrated "ICT chromophore-receptor" systems show ion-induced shifts in their electronic absorption spectra. The wavelength of observation can be used to reversibly configure the system to any of the four logic operations permissible with a single input (YES, NOT, PASS 1, PASS 0), under conditions of ion input and transmittance output. We demonstrate these with dyes integrated into Tsien's calcium receptor, 1-2. Applying multiple ion inputs to 1-2 also allows us to perform two- or three-input OR or NOR operations. The weak fluorescence output of 1 also shows YES or NOT logic depending on how it is configured by excitation and emission wavelengths. Integrated "receptor(1)-ICT chromophore-receptor(2)" systems 3-5 selectively target two ions into the receptor terminals. The ion-induced transmittance output of 3-5 can also be configured via wavelength to illustrate several logic types including, most importantly, XOR. The opposite effects of the two ions on the energy of the chromophore excited state is responsible for this behaviour. INHIBIT and REVERSE IMPLICATION are two of the other logic types seen here. Integration of XOR logic with a preceding OR operation can be arranged by using three ion inputs. The fluorescence output of these systems can be configured via wavelength to display INHIBIT or NOR logic under two-input conditions. The superposition or multiplicity of logic gate configurations is an unusual consequence of the ability to simultaneously observe multiple wavelengths.

A split-combination approach to merging knowledge bases in possibilistic logic

In this paper, we propose an adaptive approach to merging possibilistic knowledge bases that deploys multiple operators instead of a single operator in the merging process. The merging approach consists of two steps: one is called the splitting step and the other is called the combination step. The splitting step splits each knowledge base into two subbases and then in the second step, different classes of subbases are combined using different operators. Our approach is applied to knowledge bases which are self-consistent and the result of merging is also a consistent knowledge base. Two operators are proposed based on two different splitting methods. Both operators result in a possibilistic knowledge base which contains more information than that obtained by the t-conorm (such as the maximum) based merging methods. In the flat case, one of the operators provides a good alternative to syntax-based merging operators in classical logic.