Many ways to say 'no', different ways to say 'yes': Applying Q-Methodology to understand public acceptance of wind farm proposals

This paper explores the nature of public acceptance of wind farms by investigating the discourses of support and objection to a proposed offshore scheme. It reviews research into opposition to wind farms, noting previous criticisms that this has tended to provide descriptive rather than explanatory insights and as a result, has not effectively informed the policy debate. One explanation is that much of this research has been conceived within an unreflective positivist research frame, which is inadequate in dealing with the subjectivity and value-basis of public acceptance of wind farm development. The paper then takes a case study of an offshore wind farm proposal in Northern Ireland and applies Q-Methodology to identify the dominant discourse of support and objection. It is argued that this provides new insights into the nature of wind farm conflicts, points to a number or recommendations for policy functions of an example of how this methodology can act as a potential bridge between positivist and post-positivist approaches to policy analysis.

Design Methodology for Real-Time FPGA-Based Sound Synthesis

Explicit finite difference (FD) schemes can realise highly realistic physical models of musical instruments but are computationally complex. A design methodology is presented for the creation of FPGA-based micro-architectures for FD schemes which can be applied to a range of applications with varying computational requirements, excitation and output patterns and boundary conditions. It has been applied to membrane and plate-based sound producing models, resulting in faster than real-time performance on a Xilinx XC2VP50 device which is 10 to 35 times faster than general purpose and DSP processors. The models have developed in such a way to allow a wide range of interaction (by a musician) thereby leading to the possibility of creating a highly realistic digital musical instrument.

Design of silicon IP cores for biorthogonal wavelet transforms

A methodology for rapid silicon design of biorthogonal wavelet transform systems has been developed. This is based on generic, scalable architectures for the forward and inverse wavelet filters. These architectures offer efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation and interpolation. The resulting designs have been parameterised in terms of types of wavelet and wordlengths for data and coefficients. Control circuitry is embedded within these cores that allows them to be cascaded for any desired level of decomposition without any interface logic. The time to produce silicon designs for a biorthogonal wavelet system is only the time required to run synthesis and layout tools with no further design effort required. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. These designs are also portable across a range of foundries and are suitable for FPGA and PLD implementations.

Inverse Class E amplifier and oscillator phase noise characteristics

This paper gives the first experimental characterisation of the phase noise response of the recently introduced Inverse Class E topology when operated as an amplifier and then as an oscillator. The results indicate that in amplifier and oscillator modes of operation conversion efficiencies of 64%, and 42% respectively are available, and that the excess PM noise added as a consequence of saturated Class E operation results in about a 10 dB increase in PM over that expected from a small-signal Class A amplifier operating at much lower efficiency. Inverse Class E phase transfer dependence on device drain bias and flicker noise are presented in order to show, respectively, that the Inverse Class E amplifier and oscillator follow the trends predicted by conventional phase noise theory. © 2007 EuMA.

Sensitivity characteristics of inverse Class-E power amplifier

In this paper, an analysis is performed in order to determine the effects that variations in circuit component values, frequency, and duty cycle have on the performance of the newly introduced inverse Class-E amplifier. Analysis of the inverse Class-E amplifier under the generalized condition of arbitrary duty cycle is performed and it is shown that the inverse Class-E amplifier is reasonably tolerant to circuit parameter variations. When compared to the conventional Class-E amplifier the inverse Class-E amplifier offers the potential for high efficiency at increased output power as well as higher peak output power levels than are available with a conventional Class-E amplifier. Further the inverse Class-E amplifier provides more flexibility for deployment with a pulsewidth modulator as the means of producing full-carrier amplitude modulation (AM) due to its ability to operate to high AM modulation indices.

Analysis of the effect of finite d.c. blocking capacitance and finite d.c. feed inductance on the performance of inverse class-E amplifiers

The first analysis and synthesis equations for the newly introduced inverse Class-E amplifier when operated with a finite d.c. blocking capacitance and a finite d.c.-feed inductance are presented in the paper. Closed-form design equations are derived in order to establish the circuit component values required for optimum synthesis. Excellent agreement between numerical simulation results and theoretical prediction is obtained. It is shown that drain efficiency approaching 100 at a pre-specified output power level can be achieved as zero-current switching and zero-current derivative conditions are simultaneously satisfied. The proposed analysis offers the prospect for realistic MMIC implementation.

A novel shrinkage technique based on the normal inverse Gaussian density model

This paper proposes a novel image denoising technique based on the normal inverse Gaussian (NIG) density model using an extended non-negative sparse coding (NNSC) algorithm proposed by us. This algorithm can converge to feature basis vectors, which behave in the locality and orientation in spatial and frequency domain. Here, we demonstrate that the NIG density provides a very good fitness to the non-negative sparse data. In the denoising process, by exploiting a NIG-based maximum a posteriori estimator (MAP) of an image corrupted by additive Gaussian noise, the noise can be reduced successfully. This shrinkage technique, also referred to as the NNSC shrinkage technique, is self-adaptive to the statistical properties of image data. This denoising method is evaluated by values of the normalized signal to noise rate (SNR). Experimental results show that the NNSC shrinkage approach is indeed efficient and effective in denoising. Otherwise, we also compare the effectiveness of the NNSC shrinkage method with methods of standard sparse coding shrinkage, wavelet-based shrinkage and the Wiener filter. The simulation results show that our method outperforms the three kinds of denoising approaches mentioned above.

System oriented neural networks - Problem formulation, methodology and application

A novel methodology is proposed for the development of neural network models for complex engineering systems exhibiting nonlinearity. This method performs neural network modeling by first establishing some fundamental nonlinear functions from a priori engineering knowledge, which are then constructed and coded into appropriate chromosome representations. Given a suitable fitness function, using evolutionary approaches such as genetic algorithms, a population of chromosomes evolves for a certain number of generations to finally produce a neural network model best fitting the system data. The objective is to improve the transparency of the neural networks, i.e. to produce physically meaningful

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Power combining techniques into unbalanced loads for Class-E and inverse Class-E amplifiers

A power combining strategy for Class-E and inverse Class-E amplifiers operating at high frequencies such that they can operate into unbalanced loads is proposed. This power combining method is particularly important for the inverse Class-E amplifier configuration whose single-stage topology is naturally limited for small-to-medium power applications. Design examples for the power combining synthesis of classical Class-E and then inverse Class-E amplifiers with specification 3 V-1.5 W-2.5 GHz are given. For this specification, it is shown that a three-branch combiner has a natural 50 V output impedance. The resulting circuits are simulated within Agilent Advanced Design Systems environment with good agreement to theoretical prediction. Further the performance of the proposed circuits when operated in a Linear amplification using Nonlinear Components transmitter configuration whereby two-branch amplifiers are driven with constant amplitude conjugate input phase signals is investigated.