Hardware Acceleration of Background Modeling in the Compressed Domain

In intelligent video surveillance systems, scalability (of the number of simultaneous video streams) is important. Two key factors which hinder scalability are the time spent in decompressing the input video streams, and the limited computational power of the processor. This paper demonstrates how a combination of algorithmic and hardware techniques can overcome these limitations, and significantly increase the number of simultaneous streams. The techniques used are processing in the compressed domain, and exploitation of the multicore and vector processing capability of modern processors. The paper presents a system which performs background modeling, using a Mixture of Gaussians approach. This is an important first step in the segmentation of moving targets. The paper explores the effects of reducing the number of coefficients in the compressed domain, in terms of throughput speed and quality of the background modeling. The speedups achieved by exploiting compressed domain processing, multicore and vector processing are explored individually. Experiments show that a combination of all these techniques can give a speedup of 170 times on a single CPU compared to a purely serial, spatial domain implementation, with a slight gain in quality.

A Survey of Security in Software Defined Networks

The proposition of increased innovation in network applications and reduced cost for network operators has won over the networking world to the vision of Software-Defined Networking (SDN). With the excitement of holistic visibility across the network and the ability to program network devices, developers have rushed to present a range of new SDN-compliant hardware, software and services. However, amidst this frenzy of activity, one key element has only recently entered the debate: Network Security. In this article, security in SDN is surveyed presenting both the research community and industry advances in this area. The challenges to securing the network from the persistent attacker are discussed and the holistic approach to the security architecture that is required for SDN is described. Future research directions that will be key to providing network security in SDN are identified.

Lattice-based Encryption Over Standard Lattices in Hardware

Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process. In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations.
Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with lamda_2-bits of precision. Performance results are promising in comparison to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing a stronger security proof; generate 1272 encryptions per second and 4395 decryptions per second.

Experimental Study on Key Generation for Physical Layer Security in Wireless Communications

This paper presents a thorough experimental study on key generation principles, i.e. temporal variation, channel reciprocity, and spatial decorrelation, via a testbed constructed by using wireless open-access research platform (WARP). It is the first comprehensive study through (i) carrying out a number of experiments in different multipath environments, including an anechoic chamber, a reverberation chamber and an indoor office environment, which represents little, rich, and moderate multipath, respectively; (ii) considering static, object moving, and mobile scenarios in these environments, which represents different levels of channel dynamicity; (iii) studying two most popular channel parameters, i.e., channel state information and received signal strength. Through results collected from over a hundred tests, this paper offers insights to the design of a secure and efficient key generation system. We show that multipath is essential and beneficial for key generation as it increases the channel randomness. We also find that the movement of users/objects can help introduce temporal variation/randomness and help users reach an agreement on the keys. This paper complements existing research by experiments constructed by a new hardware platform.

Carbachol triggers RyR-dependent Ca(2+) release via activation of IP(3) receptors in isolated rat gastric myocytes.

Possible interactions between different intracellular Ca(2+) release channels were studied in isolated rat gastric myocytes using agonist-evoked Ca(2+) signals. Spontaneous, local Ca(2+) transients were observed in fluo-4-loaded cells with linescan confocal imaging. These were blocked by ryanodine (100 microM) but not by the inositol 1,4,5-trisphosphate receptor (IP(3)R) blocker, 2-aminoethoxydiphenyl borate (100 microM), identifying them as Ca(2+) sparks. Caffeine (10 mM) and carbachol (10 microM) initiated Ca(2+) release at sites which co-localized with each other and with any Ca(2+) spark sites. In fura-2-loaded cells extracellular 2-aminoethoxydiphenyl borate and intracellular heparin (5 mg ml(-1)) both inhibited the global cytoplasmic [Ca(2+)] transient evoked by carbachol, confirming that it was IP(3)R-dependent. 2-Aminoethoxydiphenyl borate and heparin also increased the response to caffeine. This probably reflected an increased Ca(2+) store content since 2-aminoethoxydiphenyl borate more than doubled the amplitude of transients evoked by ionomycin. Ryanodine completely abolished carbachol and caffeine responses but only reduced ionomycin transients by 30 %, suggesting that blockade of carbachol transients by ryanodine was not simply due to store depletion. Double labelling of IP(3)Rs and RyRs demonstrated extensive overlap in their distribution. These results suggest that carbachol stimulates Ca(2+) release through co-operation between IP(3)Rs and RyRs, and implicate IP(3)Rs in the regulation of Ca(2+) store content.

Risk adjustment for hospital use using social security data: cross sectional small area analysis

Objectives: To identify demographic and socioeconomic determinants of need for acute hospital treatment at small area level. To establish whether there is a relation between poverty and use of inpatient services. To devise a risk adjustment formula for distributing public funds for hospital services using, as far as possible, variables that can be updated between censuses. Design: Cross sectional analysis. Spatial interactive modelling was used to quantify the proximity of the population to health service facilities. Two stage weighted least squares regression was used to model use against supply of hospital and community services and a wide range of potential needs drivers including health, socioeconomic census variables, uptake of income support and family credit, and religious denomination. Setting: Northern Ireland. Main outcome measure: Intensity of use of inpatient services. Results: After endogeneity of supply and use was taken into account, a statistical model was produced that predicted use based on five variables: income support, family credit, elderly people living alone, all ages standardised mortality ratio, and low birth weight. The main effect of the formula produced is to move resources from urban to rural areas. Conclusions: This work has produced a population risk adjustment formula for acute hospital treatment in which four of the five variables can be updated annually rather than relying on census derived data. Inclusion of the social security data makes a substantial difference to the model and to the results produced by the formula.

Role of IP(3) in modulation of spontaneous activity in pacemaker cells of rabbit urethra.

Isolated interstitial ("pacemaker") cells from rabbit urethra were examined using the perforated-patch technique. Under voltage clamp at -60 mV, these cells fired large spontaneous transient inward currents (STICs), averaging -860 pA and >1 s in duration, which could account for urethral pacemaker activity. Spontaneous transient outward currents (STOCs) were also observed and fell into two categories, "fast" (1 s in duration). The latter were coupled to STICs, suggesting that they shared the same mechanism, while the former occurred independently at faster rates. All of these currents were abolished by cyclopiazonic acid, caffeine, or ryanodine, suggesting that they were activated by Ca(2+) release. When D-myo-inositol 1,4,5-trisphosphate (IP(3))-sensitive stores were blocked with 2-aminoethoxydiphenyl borate, the STICs and slow STOCs were abolished, but the fast STOCs remained. In contrast, the fast STOCs were more nifedipine sensitive than the STICs or the slow STOCs. These results suggest that while fast STOCs are mediated by a mechanism similar to STOCs in smooth muscle, STICs and slow STOCs are driven by IP(3). These results support the hypothesis that pacemaker activity in the urethra is driven by the IP(3)-sensitive store. PMID: 11287348 [PubMed - indexed for MEDLINE]

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.