IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

DESIGNING VLSI SIGNAL PROCESSING CHIPS USING DATA DEPENDENCE GRAPHS.

The highly structured nature of many digital signal processing operations allows these to be directly implemented as regular VLSI circuits. This feature has been successfully exploited in the design of a number of commercial chips, some examples of which are described. While many of the architectures on which such chips are based were originally derived on heuristic basis, there is an increasing interest in the development of systematic design techniques for the direct mapping of computations onto regular VLSI arrays. The purpose of this paper is to show how the the technique proposed by Kung can be readily extended to the design of VLSI signal processing chips where the organisation of computations at the level of individual data bits is of paramount importance. The technique in question allows architectures to be derived using the projection and retiming of data dependence graphs.

A co-operative formation-based collision avoidance approach for a group of autonomous vehicles (Special Issue on Adaptive Control and Signal Processing in Marine System)

This paper employs a unique decentralised cooperative control method to realise a formation-based collision avoidance strategy for a group of autonomous vehicles. In this approach, the vehicles' role in the formation and their alert and danger areas are first defined, and the formation-based intra-group and external collision avoidance methods are then proposed to translate the collision avoidance problem into the formation stability problem. The extension–decomposition–aggregation formation control method is next employed to stabilise the original and modified formations, whilst manoeuvring, and subsequently solve their collision avoidance problem indirectly. Simulation study verifies the feasibility and effectiveness of the intra-group and external collision avoidance strategy. It is demonstrated that both formation control and collision avoidance problems can be simultaneously solved if the stability of the expanded formation including external obstacles can be satisfied.

Modal Extraction for Wind Turbines using Moving Window Subspace Identification

This paper proposes a method for wind turbine mode identification using the multivariable output error statespace (MOESP) identification algorithm. The paper incorporates a fast moving window QR decomposition and propagator method from array signal processing, yielding a moving window subspace identification algorithm. The algorithm assumes that the system order is known as a priori and remains constant during identification. For the purpose of extracting modal information for turbines modelled as a linear parameter varying (LPV) system, the algorithm is applicable since a nonlinear system can be approximated as a piecewise time invariant system in consecutive data windows. The algorithm is exemplified using numerical simulations which show that the moving window algorithm can track the modal information. The paper also demonstrates that the low computational burden of the algorithm, compared to conventional batch subspace identification, has significant implications for online implementation.

Binaural Reproduction of Finite Difference Simulations Using Spherical Array Processing

Due to its efficiency and simplicity, the finite-difference time-domain method is becoming a popular choice for solving wideband, transient problems in various fields of acoustics. So far, the issue of extracting a binaural response from finite difference simulations has only been discussed in the context of embedding a listener geometry in the grid. In this paper, we propose and study a method for binaural response rendering based on a spatial decomposition of the sound field. The finite difference grid is locally sampled using a volumetric array of receivers, from which a plane wave density function is computed and integrated with free-field head related transfer functions, in the spherical harmonics domain. The volumetric array is studied in terms of numerical robustness and spatial aliasing. Analytic formulas that predict the performance of the array are developed, facilitating spatial resolution analysis and numerical binaural response analysis for a number of finite difference schemes. Particular emphasis is placed on the effects of numerical dispersion on array processing and on the resulting binaural responses. Our method is compared to a binaural simulation based on the image method. Results indicate good spatial and temporal agreement between the two methods.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.