The In Vitro Susceptibility of Biofilm Forming Medical Device Related Pathogens to Conventional Antibiotics

Minimum inhibitory concentration (MIC), minimum bactericidal concentration (MBC), and minimum biofilm eradication concentration (MBEC) and kill kinetics were established for vancomycin, rifampicin, trimethoprim, gentamicin, and ciprofloxacin against the biofilm forming bacteria Staphylococcus epidermidis (ATCC 35984), Staphylococcus aureus (ATCC 29213), Methicillin Resistant Staphylococcus aureus (MRSA) (ATCC 43300), Pseudomonas aeruginosa (PAO1), and Escherichia coli (NCTC 8196). MICs and MBCs were determined via broth microdilution in 96-well plates. MBECs were studied using the Calgary Biofilm Device. Values obtained were used to investigate the kill kinetics of conventional antimicrobials against a range of planktonic and biofilm microorganisms over a period of 24 hours. Planktonic kill kinetics were determined at 4xMIC and biofilm kill kinetics at relative MBECs. Susceptibility of microorganisms varied depending on antibiotic selected and phenotypic form of bacteria. Gram-positive planktonic isolates were extremely susceptible to vancomycin (highest MBC: 7.81 mg L−1: methicillin sensitive and resistant S. aureus) but no MBEC value was obtained against all biofilm pathogens tested (up to 1000 mg L−1). Both gentamicin and ciprofloxacin displayed the broadest spectrum of activity with MIC and MBCs in the mg L−1 range against all planktonic isolates tested and MBEC values obtained against all but S. epidermidis (ATCC 35984) and MRSA (ATCC 43300).

A device to investigate the axial strain dependence of the critical current density in superconductors

We have developed an instrument to study the behavior of the critical current density (J(c)) in superconducting wires and tapes as a function of field (mu(0)H), temperature (T), and axial applied strain (epsilon(a)). The apparatus is an improvement of similar devices that have been successfully used in our institute for over a decade. It encompasses specific advantages such as a simple sample layout, a well defined and homogeneous strain application, the possibility of investigating large compressive strains and the option of simple temperature variation, while improving the main drawback in our previous systems by increasing the investigated sample length by approximately a factor of 10. The increase in length is achieved via a design change from a straight beam section to an initially curved beam, placed perpendicular to the applied field axis in the limited diameter of a high field magnet bore. This article describes in detail the mechanical design of the device and its calibrations. Additionally initial J(c)(epsilon(a)) data, measured at liquid helium temperature, are presented for a bronze processed and for a powder-in-tube Nb3Sn superconducting wire. Comparisons are made with earlier characterizations, indicating consistent behavior of the instrument. The improved voltage resolution, resulting from the increased sample length, enables J(c) determinations at an electric field criterion E-c=10 muV/m, which is substantially lower than a criterion of E-c=100 muV/m which was possible in our previous systems. (C) 2004 American Institute of Physics.

Field Measurements of a Full Scale Tidal Device

Field testing studies are required for tidal turbine device developers to determine the performance of their turbines in tidal flows. Full-scale testing of the SCHOTTEL tidal turbine has been conducted at Queen’s University Belfast’s tidal site at Strangford Lough, NI. The device was mounted on a floating barge. Testing was conducted over 48 days, for 288 h, during flood tides in daylight hours. Several instruments were deployed, resulting in an expansive data set. The performance results from this data set are presented here. The device, rated to 50 kW at 2.75 m/s was tested in flows up to 2.5 m/s, producing up to 19 kW, when time-averaged. The thrust on the turbine reached 17 kN in the maximum flow. The maximum system efficiency of the turbine in these flows reached 35%. The test campaign was very successful and further tests may be conducted at higher flow speeds in a similar tidal environment.

IPPro: FPGA based Image Processing Processor

The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

A statistical characterization of shadowed device-to-device communications in an indoor environment

This paper presents the results of a measurement campaign aimed at characterizing and modeling the indoor radio channel between two hypothetical cellular handsets. The device-to-device channel measurements were made at 868 MHz and investigated a number of different everyday scenarios such as the devices being held at the user's heads, placed in a pocket and one of the devices placed on a desktop. The recently proposed shadowed k-μ fading model was used to characterize these channels and was shown to provide a good description of the measured data. It was also evident from the experiments, that the device-to-device communications channel is susceptible to shadowing caused by the human body.

Human body shadowing in cellular device-to-device communications: channel modeling using the shadowed κ−μ fading model

Using device-to-device communications as an underlay for cellular communications will provide an exciting opportunity to increase network capacity as well as improving spectral efficiency. The unique geometry of device-to-device links, where user equipment is often held or carried at low elevation and in close proximity to the human body, will mean that they are particularly susceptible to shadowing events caused not only by the local environment but also by the user's body. In this paper, the shadowed κ - μ fading model is proposed, which is capable of characterizing shadowed fading in wireless communication channels. In this model, the statistics of the received signal are manifested by the clustering of multipath components. Within each of these clusters, a dominant signal component with arbitrary power may exist. The resultant dominant signal component, which is formed by the phasor addition of these leading contributions, is assumed to follow a Nakagami- m distribution. The probability density function, moments, and the moment-generating function are also derived. The new model is then applied to device-to-device links operating at 868 MHz in an outdoor urban environment. It was found that shadowing of the resultant dominant component can vary significantly depending upon the position of the user equipment relative to the body and the link geometry. Overall, the shadowed κ - μ fading model is shown to provide a good fit to the field data as well as providing a useful insight into the characteristics of the received signal.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

Autonomous collective agreements as a regulatory device in European labour law:How to read Article 139 EC

This article discusses whether European social partners can derive the competence to autonomously devise European collective labour agreements from Article 139 EC (equals Article III-212 Constitution of Europe). Placing the question in the context of discussions of EU governance and private lawmaking in general, the author starts with a comparative overview of legal conceptions for collective labour agreements in Europe, focusing on three Member States' orders where their effects are not or only partly regulated by state legislation. Based on this comparison, she analyses Article 139(2) and offers a new interpretation of its provisions concerning autonomous implementation of European social partner agreements. She concludes that European social partners do have the competence to agree on a basic agreement stating the rules for European collective bargaining autonomously.

Dataflow toolset for soft-core processors on FPGA for image processing applications

With security and surveillance, there is an increasing need to be able to process image data efficiently and effectively either at source or in a large data networks. Whilst Field Programmable Gate Arrays have been seen as a key technology for enabling this, they typically use high level and/or hardware description language synthesis approaches; this provides a major disadvantage in terms of the time needed to design or program them and to verify correct operation; it considerably reduces the programmability capability of any technique based on this technology. The work here proposes a different approach of using optimised soft-core processors which can be programmed in software. In particular, the paper proposes a design tool chain for programming such processors that uses the CAL Actor Language as a starting point for describing an image processing algorithm and targets its implementation to these custom designed, soft-core processors on FPGA. The main purpose is to exploit the task and data parallelism in order to achieve the same parallelism as a previous HDL implementation but avoiding the design time, verification and debugging steps associated with such approaches.

A unique and robust single slice FPGA identification generator

In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

Histogram of oriented gradients front end processing: An FPGA based processor approach

The Field Programmable Gate Array (FPGA) implementation of the commonly used Histogram of Oriented Gradients (HOG) algorithm is explored. The HOG algorithm is employed to extract features for object detection. A key focus has been to explore the use of a new FPGA-based processor which has been targeted at image processing. The paper gives details of the mapping and scheduling factors that influence the performance and the stages that were undertaken to allow the algorithm to be deployed on FPGA hardware, whilst taking into account the specific IPPro architecture features. We show that multi-core IPPro performance can exceed that of against state-of-the-art FPGA designs by up to 3.2 times with reduced design and implementation effort and increased flexibility all on a low cost, Zynq programmable system.

Punctal plug: a medical device to treat dry eye syndrome and for sustained drug delivery to the eye

Punctal plugs (PPs) are miniature medical implants that were initially developed for the treatment of dry eyes. Since their introduction in 1975, many PPs made from different materials and designs have been developed. PPs, albeit generally successful, suffer from drawbacks such as epiphora and suppurative canaliculitis. To overcome these issues intelligent designs of PPs were proposed (e.g. SmartPLUG™ and Form Fit™). PPs are also gaining interest among pharmaceutical scientists for sustaining drug delivery to the eye. This review aims to provide an overview of PPs for dry eye treatment and drug delivery to treat a range of ocular diseases. It also discusses current challenges in using PPs for ocular diseases.